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Port to internal AXI interfaces for the debug module.

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This commit is contained in:
Jonathan Woodruff
2020-12-17 15:02:05 +00:00
parent bab989d6d2
commit 4dd0a73051
3 changed files with 14 additions and 15 deletions
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14
src_Core/Debug_Module/DM_System_Bus.bsv
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@@ -54,9 +54,9 @@ interface DM_System_Bus_IFC;
// ----------------
// Facing System
interface AXI4_Master_Synth #(Wd_MId_2x3, Wd_Addr, Wd_Data_Periph,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User) master;
interface AXI4_Master #(Wd_MId_2x3, Wd_Addr, Wd_Data_Periph,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User) master;
endinterface
// ================================================================
@@ -197,10 +197,8 @@ module mkDM_System_Bus (DM_System_Bus_IFC);
// ----------------------------------------------------------------
// Interface to memory fabric
AXI4_Master_Xactor#(Wd_MId_2x3, Wd_Addr, Wd_Data_Periph,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User)
master_xactor <- mkAXI4_Master_Xactor;
let master_xactor <- mkAXI4ShimFF;
// ----------------------------------------------------------------
// System Bus state
@@ -680,7 +678,7 @@ module mkDM_System_Bus (DM_System_Bus_IFC);
// ----------------
// Facing System
interface AXI4_Master_IFC master = master_xactor.masterSynth;
interface master = master_xactor.master;
endmodule
// ================================================================

8
src_Core/Debug_Module/Debug_Module.bsv
View File

@@ -155,9 +155,9 @@ interface Debug_Module_IFC;
interface Client #(Bool, Bool) ndm_reset_client;
// Read/Write RISC-V memory
interface AXI4_Master_Synth #(Wd_MId_2x3, Wd_Addr, Wd_Data_Periph,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User) master;
interface AXI4_Master #(Wd_MId_2x3, Wd_Addr, Wd_Data_Periph,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User) master;
endinterface
// ================================================================
@@ -481,7 +481,7 @@ module mkDebug_Module (Debug_Module_IFC);
interface Client ndm_reset_client = dm_run_control.ndm_reset_client;
// Read/Write RISC-V memory
interface AXI4_Master_IFC master = dm_system_bus.master;
interface master = dm_system_bus.master;
endmodule
// ================================================================