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RenameStage.bsv: Fix single-step when only one instruction available

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If we never look at the second instruction in the FIFO from the fetch
unit when successfully renaming the first, we do not end up setting
debug_step and thus we will not halt on the next instruction but some
time later. Instead, check for single-stepping at the end of renaming
the first instruction.
This commit is contained in:
Jessica Clarke
2020-04-02 04:20:13 +01:00
parent 6cfedfe1c8
commit 4e0bd06a10
1 changed files with 7 additions and 7 deletions
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14
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
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@@ -843,13 +843,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
Addr fallthrough_pc = ((orig_inst[1:0] == 2'b11) ? pc + 4 : pc + 2);
`ifdef INCLUDE_GDB_CONTROL
if ((i != 0) && (csrf.dcsr_step_bit == 1'b1)) begin
stop = True;
debug_step = True;
end
`endif
// check for wrong path, if wrong path, don't process it, leave to the other rule in next cycle
if(!epochManager.checkEpoch[i].check(main_epoch)) begin
stop = True;
@@ -1104,6 +1097,13 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
if(spec_tag matches tagged Valid .t) begin
spec_bits = spec_bits | (1 << t);
end
`ifdef INCLUDE_GDB_CONTROL
if ((i == 0) && (csrf.dcsr_step_bit == 1'b1)) begin
stop = True;
debug_step = True;
end
`endif
end
end
end