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Updated so SoC addrs are taken from SoC_Map.bsv

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This commit is contained in:
rsnikhil
2019-04-01 14:34:49 -04:00
parent 113f888d37
commit 4e305ac98d
36 changed files with 14145 additions and 13788 deletions
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27
src_Core/CPU/Proc.bsv
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@@ -27,12 +27,13 @@ package Proc;
// ================================================================
// BSV lib imports
import Vector::*;
import GetPut::*;
import ClientServer::*;
import Connectable::*;
import FIFOF :: *;
import ConfigReg :: *;
import Assert :: *;
import Vector :: *;
import GetPut :: *;
import ClientServer :: *;
import Connectable :: *;
import FIFOF :: *;
import ConfigReg :: *;
// ----------------
// BSV additional libs
@@ -65,15 +66,17 @@ import Performance::*;
import ISA_Decls :: *;
import AXI4_Types :: *;
import Fabric_Defs :: *;
import Core :: *;
import Proc_IFC :: *;
import MMIOPlatform :: *;
import LLC_AXI4_Adapter :: *;
import MMIO_AXI4_Adapter :: *;
import SoC_Map :: *;
import AXI4_Types :: *;
import Fabric_Defs :: *;
`ifdef INCLUDE_GDB_CONTROL
import DM_CPU_Req_Rsp :: *;
`endif
@@ -86,6 +89,12 @@ import TV_Info :: *;
(* synthesize *)
module mkProc (Proc_IFC);
// Check that RISCY-OOO and Bluespec defs of boot rom size are the same
staticAssert ( (soc_map_struct.boot_rom_addr_size == fromInteger (valueOf (TExp #(LgBootRomBytes)))),
"Boot ROM size def mismatch: ProcConfig.bsv:LgBootRomBytes vs. SoC_Map.bsv:soc_map_struct.boot_rom_addr_size");
// ----------------
// cores
Vector#(CoreNum, Core) core = ?;
for(Integer i = 0; i < valueof(CoreNum); i = i+1) begin

18
src_Core/Core/CoreW.bsv
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@@ -98,6 +98,10 @@ module mkCoreW (CoreW_IFC #(N_External_Interrupt_Sources));
Debug_Module_IFC debug_module <- mkDebug_Module;
`endif
// HTIF locations (for debugging only)
Reg #(Bit #(64)) rg_tohost_addr <- mkReg (0);
Reg #(Bit #(64)) rg_fromhost_addr <- mkReg (0);
// ================================================================
// RESET
// There are two sources of reset requests to the CPU: externally
@@ -159,10 +163,9 @@ module mkCoreW (CoreW_IFC #(N_External_Interrupt_Sources));
f_reset_rsps.enq (?);
// Start running the cores
Bit #(64) startpc = 'h_0000_1000; // TODO: fixup
Bit #(64) tohostAddr = 'h_8000_1000; // TODO: fixup
Bit #(64) fromhostAddr = 0;
proc.start (startpc, tohostAddr, fromhostAddr);
proc.start (soc_map_struct.pc_reset_value,
rg_tohost_addr,
rg_fromhost_addr);
$display ("%0d: Core.rl_cpu_hart0_reset_complete; started running proc", cur_cycle);
endrule
@@ -334,13 +337,18 @@ module mkCoreW (CoreW_IFC #(N_External_Interrupt_Sources));
// INTERFACE
// ----------------------------------------------------------------
// Debugging: set core's verbosity
// Debugging: set core's verbosity, htif addrs
method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay);
// Warning: ignoring logdelay
proc.set_verbosity (verbosity);
endmethod
method Action set_htif_addrs (Bit #(64) tohost_addr, Bit #(64) fromhost_addr);
rg_tohost_addr <= tohost_addr;
rg_fromhost_addr <= fromhost_addr;
endmethod
// ----------------------------------------------------------------
// Soft reset

4
src_Core/Core/CoreW_IFC.bsv
View File

@@ -46,10 +46,12 @@ import Debug_Module :: *;
interface CoreW_IFC #(numeric type t_n_interrupt_sources);
// ----------------------------------------------------------------
// Debugging: set core's verbosity
// Debugging: set core's verbosity, htif addrs
method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay);
method Action set_htif_addrs (Bit #(64) tohost_addr, Bit #(64) fromhost_addr);
// ----------------------------------------------------------------
// Soft reset

11
src_Core/RISCY_OOO/procs/lib/MMIOAddrs.bsv
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@@ -25,6 +25,8 @@ import Types::*;
import ProcTypes::*;
import CCTypes::*;
import SoC_Map :: *; // Bluespec setup
// data aligned addr
typedef TSub#(AddrSz, LgDataSzBytes) DataAlignedAddrSz;
typedef Bit#(DataAlignedAddrSz) DataAlignedAddr;
@@ -32,12 +34,20 @@ typedef Bit#(DataAlignedAddrSz) DataAlignedAddr;
function DataAlignedAddr getDataAlignedAddr(Addr a) = truncateLSB(a);
// base addr for each MMIO reg/device (aligned to Data)
/* ORIGINAL MIT SETUP
DataAlignedAddr bootRomBaseAddr = getDataAlignedAddr(64'h00001000);
DataAlignedAddr memLoaderBaseAddr = getDataAlignedAddr(64'h01000000);
DataAlignedAddr msipBaseAddr = getDataAlignedAddr(64'h02000000);
DataAlignedAddr mtimecmpBaseAddr = getDataAlignedAddr(64'h02004000);
DataAlignedAddr mtimeBaseAddr = getDataAlignedAddr(64'h0200bff8);
DataAlignedAddr mainMemBaseAddr = getDataAlignedAddr(64'h80000000);
*/
DataAlignedAddr bootRomBaseAddr = getDataAlignedAddr(soc_map_struct.boot_rom_addr_base);
DataAlignedAddr msipBaseAddr = getDataAlignedAddr(soc_map_struct.near_mem_io_addr_base + 64'h_0000_0000);
DataAlignedAddr mtimecmpBaseAddr = getDataAlignedAddr(soc_map_struct.near_mem_io_addr_base + 64'h_0000_4000);
DataAlignedAddr mtimeBaseAddr = getDataAlignedAddr(soc_map_struct.near_mem_io_addr_base + 64'h_0000_bff8);
DataAlignedAddr mainMemBaseAddr = getDataAlignedAddr(soc_map_struct.mem0_controller_addr_base);
// XXX Each msip reg is 32-bit, while mtime and each mtimecmp are 64-bit. We
// assume Data is 64-bit. We hard code this relation in all MMIO logic.
@@ -50,7 +60,6 @@ DataAlignedAddr mainMemBaseAddr = getDataAlignedAddr(64'h80000000);
// (aligned to Data)
DataAlignedAddr bootRomBoundAddr = bootRomBaseAddr +
fromInteger(valueof(TExp#(LgBootRomSzData)));
DataAlignedAddr memLoaderBoundAddr = memLoaderBaseAddr + 2;
DataAlignedAddr msipBoundAddr = msipBaseAddr +
fromInteger(valueof(TDiv#(CoreNum, 2)));
DataAlignedAddr mtimecmpBoundAddr = mtimecmpBaseAddr +