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Only train from branches that have all previous branches resolved.

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This commit is contained in:
Jonathan Woodruff
2021-11-12 17:55:04 +00:00
parent 04a5d82ff0
commit 54c0ccadf0
2 changed files with 34 additions and 24 deletions
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20
src_Core/CPU/Core.bsv
View File

@@ -82,6 +82,7 @@ import ReorderBufferSynth::*;
import Scoreboard::*;
import ScoreboardSynth::*;
import SpecTagManager::*;
import SpecFifo::*;
import Fpu::*;
import MulDiv::*;
import ReservationStationEhr::*;
@@ -345,11 +346,16 @@ module mkCore#(CoreId coreId)(Core);
for(Integer i = 0; i < valueof(FpuMulDivExeNum); i = i+1) begin
fpuMulDivSpecUpdate[i] = fix.fpuMulDivExeIfc[i].specUpdate;
end
Vector#(AluExeNum, SpecFifo#(NumInstTags, FetchTrainBP, 1, 1)) trainBPQ <- replicateM(mkSpecFifoCF(True));
Vector#(AluExeNum, SpeculationUpdate) btqSpecUpdate;
for(Integer i = 0; i < valueof(AluExeNum); i = i+1) begin
btqSpecUpdate[i] = trainBPQ[i].specUpdate;
end
GlobalSpecUpdate#(CorrectSpecPortNum, ConflictWrongSpecPortNum) globalSpecUpdate <- mkGlobalSpecUpdate(
joinSpeculationUpdate(
append(append(vec(regRenamingTable.specUpdate,
specTagManager.specUpdate,
fix.memExeIfc.specUpdate), aluSpecUpdate), fpuMulDivSpecUpdate)
append(append(append(vec(regRenamingTable.specUpdate,
specTagManager.specUpdate,
fix.memExeIfc.specUpdate), aluSpecUpdate), fpuMulDivSpecUpdate), btqSpecUpdate)
),
rob.specUpdate
);
@@ -379,7 +385,6 @@ module mkCore#(CoreId coreId)(Core);
endaction
endfunction
Vector#(AluExeNum, FIFO#(FetchTrainBP)) trainBPQ <- replicateM(mkFIFO);
Vector#(AluExeNum, AluExePipeline) aluExe;
for(Integer i = 0; i < valueof(AluExeNum); i = i+1) begin
Vector#(2, SendBypass) sendBypassIfc; // exe and finish
@@ -408,7 +413,7 @@ module mkCore#(CoreId coreId)(Core);
method rob_getPredPC = rob.getOrigPredPC[i].get;
method rob_getOrig_Inst = rob.getOrig_Inst[i].get;
method rob_setExecuted = rob.setExecuted_doFinishAlu[i].set;
method fetch_train_predictors = toPut(trainBPQ[i]).put;
method fetch_train_predictors = trainBPQ[i].enq;
method setRegReadyAggr = writeAggr(aluWrAggrPort(i));
interface sendBypass = sendBypassIfc;
method writeRegFile = writeCons(aluWrConsPort(i));
@@ -448,8 +453,9 @@ module mkCore#(CoreId coreId)(Core);
endinterface);
aluExe[i] <- mkAluExePipeline(aluExeInput);
// truly call fetch method to train branch predictor
rule doFetchTrainBP;
let train <- toGet(trainBPQ[i]).get;
rule doFetchTrainBP(trainBPQ[i].first.spec_bits == 0);
let train = trainBPQ[i].first.data;
trainBPQ[i].deq;
fetchStage.train_predictors(
train.pc, train.nextPc, train.iType, train.taken,
train.dpTrain, train.mispred, train.isCompressed

38
src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
View File

@@ -184,7 +184,7 @@ interface AluExeInput;
`endif
);
// Fetch stage
method Action fetch_train_predictors(FetchTrainBP train);
method Action fetch_train_predictors(ToSpecFifo#(FetchTrainBP) train);
// global broadcast methods
// set aggressive sb & wake up inst in RS
@@ -472,14 +472,16 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
inIfc.redirect(cast(x.controlFlow.nextPc), validValue(x.spec_tag), x.tag);
// must be a branch, train branch predictor
doAssert(x.iType == Jr || x.iType == CJALR || x.iType == CCall || x.iType == Br, "only jr, br, cjalr, and ccall can mispredict");
inIfc.fetch_train_predictors(FetchTrainBP {
pc: cast(x.controlFlow.pc),
nextPc: cast(x.controlFlow.nextPc),
iType: x.iType,
taken: x.controlFlow.taken,
dpTrain: x.dpTrain,
mispred: True,
isCompressed: x.isCompressed
inIfc.fetch_train_predictors(ToSpecFifo {
data: FetchTrainBP {
pc: cast(x.controlFlow.pc),
nextPc: cast(x.controlFlow.nextPc),
iType: x.iType,
taken: x.controlFlow.taken,
dpTrain: x.dpTrain,
mispred: True,
isCompressed: x.isCompressed},
spec_bits: exeToFin.spec_bits
});
`ifdef PERF_COUNT
// performance counter
@@ -501,14 +503,16 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
// since we can only do 1 training in a cycle, split the rule
// XXX not training JAL, reduce chance of conflicts
if(x.iType == Jr || x.iType == CJALR || x.iType == CCall || x.iType == Br) begin
inIfc.fetch_train_predictors(FetchTrainBP {
pc: cast(x.controlFlow.pc),
nextPc: cast(x.controlFlow.nextPc),
iType: x.iType,
taken: x.controlFlow.taken,
dpTrain: x.dpTrain,
mispred: False,
isCompressed: x.isCompressed
inIfc.fetch_train_predictors(ToSpecFifo {
data: FetchTrainBP {
pc: cast(x.controlFlow.pc),
nextPc: cast(x.controlFlow.nextPc),
iType: x.iType,
taken: x.controlFlow.taken,
dpTrain: x.dpTrain,
mispred: False,
isCompressed: x.isCompressed},
spec_bits: exeToFin.spec_bits
});
end
end