Integration of Debug_Module basically complete (except resume-after-break, details follow)
Stop, set breakpoint: working, stopping successfully. Step: working: stops after a step. Continue (resume) working after Stop and Step, but not after stop by breakpoint (needs debugging) Read/Write GPRs, FPRs, CSRs, memory working.
This commit is contained in:
rsnikhil
@@ -159,20 +159,11 @@ interface Core;
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method Action setDEIP (Bit #(1) v);
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`ifdef INCLUDE_GDB_CONTROL
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method Action debug_halt;
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(* always_ready *)
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method Bool is_debug_halted;
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method Action debug_resume;
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interface Server #(DM_CPU_Req #(5, 64), DM_CPU_Rsp #(64)) hart0_gpr_mem_server;
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interface Server #(Bool, Bool) hart0_run_halt_server;
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interface Server #(DM_CPU_Req #(5, 64), DM_CPU_Rsp #(64)) hart0_gpr_mem_server;
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`ifdef ISA_F
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// FPR access
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interface Server #(DM_CPU_Req #(5, 64), DM_CPU_Rsp #(64)) hart0_fpr_mem_server;
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interface Server #(DM_CPU_Req #(5, 64), DM_CPU_Rsp #(64)) hart0_fpr_mem_server;
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`endif
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// CSR access
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interface Server #(DM_CPU_Req #(12, 64), DM_CPU_Rsp #(64)) hart0_csr_mem_server;
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`endif
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endinterface
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@@ -188,6 +179,7 @@ endinterface
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typedef enum {
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`ifdef INCLUDE_GDB_CONTROL
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CORE_HALTING,
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CORE_HALTED,
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`endif
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CORE_RUNNING
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@@ -744,8 +736,8 @@ module mkCore#(CoreId coreId)(Core);
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`ifdef INCLUDE_GDB_CONTROL
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if (commitStage.is_debug_halted) begin
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started <= False;
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rg_core_run_state <= CORE_HALTED;
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$display ("%0d: %m.rule readyToFetch: debug halt", cur_cycle);
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rg_core_run_state <= CORE_HALTING;
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$display ("%0d: %m.rule readyToFetch: halting for debug mode", cur_cycle);
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end
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`endif
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endrule
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@@ -1031,7 +1023,9 @@ module mkCore#(CoreId coreId)(Core);
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// ================================================================
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// DEBUG MODULE INTERFACE
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// ----------------
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Bool show_DM_interactions = True; // for debugging the interactions
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// ----------------------------------------------------------------
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// Debug Module GPR read/write
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FIFOF #(DM_CPU_Req #(5, 64)) f_gpr_reqs <- mkFIFOF1;
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@@ -1053,7 +1047,8 @@ module mkCore#(CoreId coreId)(Core);
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let rsp = DM_CPU_Rsp {ok: True, data: data_out};
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f_gpr_rsps.enq (rsp);
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// if (cur_verbosity > 1)
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if (show_DM_interactions)
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$display ("%0d: %m.rl_debug_read_gpr: reg %0d => 0x%0h", cur_cycle, regnum, data_out);
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endrule
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@@ -1071,26 +1066,26 @@ module mkCore#(CoreId coreId)(Core);
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let rename_result = regRenamingTable.rename[0].getRename (arch_regs);
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let phy_rindx = fromMaybe (?, rename_result.phy_regs.src1);
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rf.write [debuggerPort].wr (phy_rindx, data_in);
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$display ("%m.gpr_write (%0d, %0x), phy_rindx %0d", regnum, data_in, phy_rindx);
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let rsp = DM_CPU_Rsp {ok: True, data: ?};
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f_gpr_rsps.enq (rsp);
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// if (cur_verbosity > 1)
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$display ("%0d: %m.rl_debug_write_gpr: reg %0d <= 0x%0h", cur_cycle, regnum, data_in);
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if (show_DM_interactions)
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$display ("%0d: %m.rl_debug_gpr_write: reg %0d <= 0x%0h (phy_rindx = %0d)",
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cur_cycle, regnum, data_in, phy_rindx);
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endrule
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rule rl_debug_gpr_access_busy (rg_core_run_state != CORE_HALTED);
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rule rl_debug_gpr_access_busy (rg_core_run_state == CORE_RUNNING);
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let req <- pop (f_gpr_reqs);
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let rsp = DM_CPU_Rsp {ok: False, data: ?};
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f_gpr_rsps.enq (rsp);
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// if (cur_verbosity > 1)
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if (show_DM_interactions)
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$display ("%0d: %m.rl_debug_gpr_access_busy", cur_cycle);
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endrule
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`ifdef ISA_F
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// ----------------
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// ----------------------------------------------------------------
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// Debug Module FPR read/write
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FIFOF #(DM_CPU_Req #(5, 64)) f_fpr_reqs <- mkFIFOF1;
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@@ -1112,7 +1107,8 @@ module mkCore#(CoreId coreId)(Core);
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let rsp = DM_CPU_Rsp {ok: True, data: data_out};
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f_fpr_rsps.enq (rsp);
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// if (cur_verbosity > 1)
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if (show_DM_interactions)
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$display ("%0d: %m.rl_debug_read_fpr: reg %0d => 0x%0h", cur_cycle, regnum, data_out);
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endrule
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@@ -1130,26 +1126,28 @@ module mkCore#(CoreId coreId)(Core);
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let rename_result = regRenamingTable.rename[0].getRename (arch_regs);
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let phy_rindx = fromMaybe (?, rename_result.phy_regs.src1);
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rf.write [debuggerPort].wr (phy_rindx, data_in);
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$display ("%m.gpr_write (%0d, %0x), phy_rindx %0d", regnum, data_in, phy_rindx);
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let rsp = DM_CPU_Rsp {ok: True, data: ?};
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f_fpr_rsps.enq (rsp);
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// if (cur_verbosity > 1)
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$display ("%0d: %m.rl_debug_write_fpr: reg %0d <= 0x%0h", cur_cycle, regnum, data_in);
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if (show_DM_interactions)
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$display ("%0d: %m.rl_debug_write_fpr: reg %0d <= 0x%0h (phy_rindx %0d)",
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cur_cycle, regnum, data_in, phy_rindx);
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endrule
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rule rl_debug_fpr_access_busy (rg_core_run_state != CORE_HALTED);
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rule rl_debug_fpr_access_busy ( (rg_core_run_state == CORE_RUNNING)
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&& f_fpr_reqs.notEmpty);
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let req <- pop (f_fpr_reqs);
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let rsp = DM_CPU_Rsp {ok: False, data: ?};
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f_fpr_rsps.enq (rsp);
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// if (cur_verbosity > 1)
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if (show_DM_interactions)
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$display ("%0d: %m.rl_debug_fpr_access_busy", cur_cycle);
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endrule
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`endif
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// ----------------
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// ----------------------------------------------------------------
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// Debug Module CSR read/write
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// Debugger CSR read/write request/response
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@@ -1164,7 +1162,8 @@ module mkCore#(CoreId coreId)(Core);
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let rsp = DM_CPU_Rsp {ok: True, data: data_out};
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f_csr_rsps.enq (rsp);
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// if (cur_verbosity > 1)
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if (show_DM_interactions)
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$display ("%0d: %m.rl_debug_read_csr: csr %0d => 0x%0h", cur_cycle, csr_addr, data_out);
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endrule
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@@ -1178,19 +1177,107 @@ module mkCore#(CoreId coreId)(Core);
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let rsp = DM_CPU_Rsp {ok: True, data: ?};
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f_csr_rsps.enq (rsp);
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// if (cur_verbosity > 1)
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if (show_DM_interactions)
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$display ("%0d: %m.rl_debug_write_csr: csr 0x%0h <= 0x%0h", cur_cycle, csr_addr, data_in);
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endrule
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rule rl_debug_csr_access_busy (rg_core_run_state != CORE_HALTED);
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rule rl_debug_csr_access_busy (rg_core_run_state == CORE_RUNNING);
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let req <- pop (f_csr_reqs);
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let rsp = DM_CPU_Rsp {ok: False, data: ?};
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f_csr_rsps.enq (rsp);
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// if (cur_verbosity > 1)
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if (show_DM_interactions)
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$display ("%0d: %m.rl_debug_csr_access_busy", cur_cycle);
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endrule
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// ----------------------------------------------------------------
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// Debug Module run-halt control
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FIFOF #(Bool) f_run_halt_reqs <- mkFIFOF;
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FIFOF #(Bool) f_run_halt_rsps <- mkFIFOF;
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Reg #(Bool) rg_sent_halt_rsp <- mkReg (False);
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// ----------------
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// Debug Module Halt control
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rule rl_debug_halt_req ( (rg_core_run_state == CORE_RUNNING)
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&& (f_run_halt_reqs.first == False));
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f_run_halt_reqs.deq;
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// Debugger 'halt' request (e.g., GDB '^C' command)
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// This is initiated just like an interrupt.
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renameStage.debug_halt_req;
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rg_sent_halt_rsp <= False;
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if (show_DM_interactions)
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$display ("%0d: %m.rl_debug_halt_req", cur_cycle);
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endrule
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rule rl_debug_halt_req_already_halted ( (rg_core_run_state != CORE_RUNNING)
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&& (f_run_halt_reqs.first == False));
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f_run_halt_reqs.deq;
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// Notify debugger that we've 'halted'
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f_run_halt_rsps.enq (False);
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if (show_DM_interactions)
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$display ("%0d: %m.rl_debug_halt_req_already_halted", cur_cycle);
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endrule
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// Monitors when we've reached halted state while running
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// (due to halt, step or EBREAK) and notifies DM
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rule rl_debug_halted (rg_core_run_state == CORE_HALTING);
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// Notify debugger that we've halted
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f_run_halt_rsps.enq (False);
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rg_core_run_state <= CORE_HALTED;
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if (show_DM_interactions)
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$display ("%0d: %m.rl_debug_halted", cur_cycle);
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endrule
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// ----------------
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// Debug Module Resume (run) control
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// Resume command when in debug mode
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rule rl_debug_resume ( (rg_core_run_state == CORE_HALTED)
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&& (f_run_halt_reqs.first == True)
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// prioritise gpr/fpr/csr read/write requests before resuming
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&& (! f_gpr_reqs.notEmpty)
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`ifdef ISA_F
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&& (! f_fpr_reqs.notEmpty)
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`endif
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&& (! f_csr_reqs.notEmpty));
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f_run_halt_reqs.deq;
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let startpc = csrf.dpc_read;
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fetchStage.redirect (startpc);
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renameStage.debug_resume;
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commitStage.debug_resume;
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started <= True;
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rg_core_run_state <= CORE_RUNNING;
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// Notify debugger that we've started running
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f_run_halt_rsps.enq (True);
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if (show_DM_interactions)
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$display ("%0d: %m.debug_resume, dpc = 0x%0h", cur_cycle, startpc);
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endrule
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// Run command when already running
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rule rl_debug_run_redundant ( (rg_core_run_state == CORE_RUNNING)
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&& (f_run_halt_reqs.first == True));
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f_run_halt_reqs.deq;
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// Notify debugger that we're running
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f_run_halt_rsps.enq (True);
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if (show_DM_interactions)
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$display ("%0d: %m.rl_debug_run_redundant", cur_cycle);
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endrule
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// ================================================================
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`endif
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@@ -1276,35 +1363,12 @@ module mkCore#(CoreId coreId)(Core);
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method Action setDEIP (v) = csrf.setDEIP (v);
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`ifdef INCLUDE_GDB_CONTROL
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method Action debug_halt () if (started && (rg_core_run_state == CORE_RUNNING));
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$display ("%0d: %m.debug_halt", cur_cycle);
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renameStage.debug_halt; // start the halt protocol
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endmethod
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method Bool is_debug_halted;
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return (rg_core_run_state == CORE_HALTED);
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endmethod
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method Action debug_resume () if (rg_core_run_state == CORE_HALTED);
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let startpc = csrf.dpc_read;
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fetchStage.redirect (startpc);
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renameStage.debug_resume;
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commitStage.debug_resume;
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started <= True;
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rg_core_run_state <= CORE_RUNNING;
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$display ("%0d: %m.debug_resume, dpc = 0x%0h", cur_cycle, startpc);
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endmethod
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interface Server hart0_gpr_mem_server = toGPServer (f_gpr_reqs, f_gpr_rsps);
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interface Server hart0_run_halt_server = toGPServer (f_run_halt_reqs, f_run_halt_rsps);
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interface Server hart0_gpr_mem_server = toGPServer (f_gpr_reqs, f_gpr_rsps);
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`ifdef ISA_F
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interface Server hart0_fpr_mem_server = toGPServer (f_fpr_reqs, f_fpr_rsps);
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interface Server hart0_fpr_mem_server = toGPServer (f_fpr_reqs, f_fpr_rsps);
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`endif
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// CSR access
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interface Server hart0_csr_mem_server = toGPServer (f_csr_reqs, f_csr_rsps);
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interface Server hart0_csr_mem_server = toGPServer (f_csr_reqs, f_csr_rsps);
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`endif
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endmodule
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@@ -85,23 +85,6 @@ import TV_Info :: *;
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import DM_CPU_Req_Rsp :: *;
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`endif
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// ================================================================
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// CPU run-states
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// TODO: Reset from GDB etc.
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typedef enum {CPU_RUNNING // Normal operation
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`ifdef INCLUDE_GDB_CONTROL
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,
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CPU_ENTERING_DEBUG_MODE, // On GDB breakpoint, while waiting for fence completion
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CPU_DEBUG_MODE // Halted for debugger
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`endif
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} CPU_State
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deriving (Eq, Bits, FShow);
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function Bool fn_is_running (CPU_State cpu_state);
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return (cpu_state == CPU_RUNNING);
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endfunction
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// ================================================================
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(* synthesize *)
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@@ -120,27 +103,12 @@ module mkProc (Proc_IFC);
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// Verbosity: 0=quiet; 1=instruction trace; 2=more detail
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Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (0);
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// ----------------
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// CPU run/debug states
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Reg #(CPU_State) rg_state <- mkReg (CPU_RUNNING);
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// ----------------
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// Reset requests and responses (TODO: to be implemented)
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FIFOF #(Bit #(0)) f_reset_reqs <- mkFIFOF;
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FIFOF #(Bit #(0)) f_reset_rsps <- mkFIFOF;
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`ifdef INCLUDE_GDB_CONTROL
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// ----------------
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// Communication to/from External debug module (TODO: to be implemented)
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// Debugger run-control
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FIFOF #(Bool) f_run_halt_reqs <- mkFIFOF;
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FIFOF #(Bool) f_run_halt_rsps <- mkFIFOF;
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`endif
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// ----------------
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// Tandem Verification (TODO: to be implemented)
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@@ -182,7 +150,7 @@ module mkProc (Proc_IFC);
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end
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// Note: mkLLCDmaConnect is Toooba version, different from riscy-ooo version
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let llc__mem_server <- mkLLCDmaConnect(llc.dma, tlbToMem);
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let llc_mem_server <- mkLLCDmaConnect(llc.dma, tlbToMem);
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// ================================================================
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// interface Back-side of LLC to AXI4
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@@ -278,85 +246,6 @@ module mkProc (Proc_IFC);
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end
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endrule
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// ================================================================
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// ================================================================
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// ================================================================
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// DEBUGGER ACCESS
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`ifdef INCLUDE_GDB_CONTROL
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// ----------------
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// Debug Module Run (resume) control
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// Run command when in debug mode
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rule rl_debug_run ((f_run_halt_reqs.first == True)
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// && (! f_csr_reqs.notEmpty)
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&& (rg_state == CPU_DEBUG_MODE));
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// if (cfg_verbosity > 1)
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$display ("%0d: %m.rl_debug_run", cur_cycle);
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f_run_halt_reqs.deq;
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core[0].debug_resume;
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rg_state <= CPU_RUNNING;
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// Notify debugger that we've started running
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f_run_halt_rsps.enq (True);
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endrule
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// Run command when already running
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rule rl_debug_run_redundant ((f_run_halt_reqs.first == True)
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// && (! f_csr_reqs.notEmpty)
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&& fn_is_running (rg_state));
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// if (cfg_verbosity > 1)
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$display ("%0d: %m.rl_debug_run_redundant", cur_cycle);
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f_run_halt_reqs.deq;
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// Notify debugger that we're running
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f_run_halt_rsps.enq (True);
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endrule
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// ----------------
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// Debug Module Halt control
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rule rl_debug_halt ((f_run_halt_reqs.first == False) && fn_is_running (rg_state));
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// if (cfg_verbosity > 1)
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$display ("%0d: %m.rl_debug_halt", cur_cycle);
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f_run_halt_reqs.deq;
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// Debugger 'halt' request (e.g., GDB '^C' command)
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||||
// This is just like an interrupt.
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core[0].debug_halt;
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endrule
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||||
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// Monitors when we've reached halted state while running (halt,
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// step or EBREAK) and notifies DM
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rule rl_debug_halted (fn_is_running (rg_state) && core [0].is_debug_halted);
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// Notify debugger that we've halted
|
||||
f_run_halt_rsps.enq (False);
|
||||
// Stop executing rules until ready to restart from debugger
|
||||
rg_state <= CPU_DEBUG_MODE;
|
||||
|
||||
// if (cfg_verbosity > 1)
|
||||
$display ("%0d: %m.rl_debug_halted", cur_cycle);
|
||||
endrule
|
||||
|
||||
rule rl_debug_halt_redundant ((f_run_halt_reqs.first == False) && (! fn_is_running (rg_state)));
|
||||
// if (cfg_verbosity > 1)
|
||||
$display ("%0d: %m.rl_debug_halt_redundant", cur_cycle);
|
||||
|
||||
f_run_halt_reqs.deq;
|
||||
|
||||
// Notify debugger that we've 'halted'
|
||||
f_run_halt_rsps.enq (False);
|
||||
|
||||
$display ("%0d: %m.rl_debug_halt_redundant: CPU already halted; state = ",
|
||||
cur_cycle, fshow (rg_state));
|
||||
endrule
|
||||
|
||||
`endif
|
||||
|
||||
// ================================================================
|
||||
// ================================================================
|
||||
// ================================================================
|
||||
@@ -430,27 +319,23 @@ module mkProc (Proc_IFC);
|
||||
// Optional interface to Debug Module
|
||||
|
||||
`ifdef INCLUDE_GDB_CONTROL
|
||||
// run-control, other
|
||||
interface Server hart0_server_run_halt = toGPServer (f_run_halt_reqs, f_run_halt_rsps);
|
||||
// run/halt, gpr, mem and csr control goes to core
|
||||
interface Server hart0_run_halt_server = core [0].hart0_run_halt_server;
|
||||
interface Server hart0_gpr_mem_server = core[0].hart0_gpr_mem_server;
|
||||
`ifdef ISA_F
|
||||
interface Server hart0_fpr_mem_server = core[0].hart0_fpr_mem_server;
|
||||
`endif
|
||||
interface Server hart0_csr_mem_server = core[0].hart0_csr_mem_server;
|
||||
|
||||
// mem access goes to LLC (stays coherent with CPU pipeline).
|
||||
interface debug_module_mem_server = llc_mem_server;
|
||||
|
||||
// We don't implement 'other' functionality
|
||||
interface Put hart0_put_other_req;
|
||||
method Action put (Bit #(4) req);
|
||||
cfg_verbosity <= req;
|
||||
endmethod
|
||||
endinterface
|
||||
|
||||
// GPR access
|
||||
interface Server hart0_gpr_mem_server = core[0].hart0_gpr_mem_server;
|
||||
|
||||
`ifdef ISA_F
|
||||
// FPR access
|
||||
interface Server hart0_fpr_mem_server = core[0].hart0_fpr_mem_server;
|
||||
`endif
|
||||
|
||||
// CSR access
|
||||
interface Server hart0_csr_mem_server = core[0].hart0_csr_mem_server;
|
||||
|
||||
interface debug_module_mem_server = llc__mem_server;
|
||||
`endif
|
||||
|
||||
endmodule: mkProc
|
||||
|
||||
@@ -85,22 +85,16 @@ interface Proc_IFC;
|
||||
// Optional interface to Debug Module
|
||||
|
||||
`ifdef INCLUDE_GDB_CONTROL
|
||||
// run-control, other
|
||||
interface Server #(Bool, Bool) hart0_server_run_halt;
|
||||
interface Put #(Bit #(4)) hart0_put_other_req;
|
||||
|
||||
// GPR access
|
||||
interface Server #(Bool, Bool) hart0_run_halt_server;
|
||||
interface Server #(DM_CPU_Req #(5, XLEN), DM_CPU_Rsp #(XLEN)) hart0_gpr_mem_server;
|
||||
|
||||
`ifdef ISA_F
|
||||
// FPR access
|
||||
interface Server #(DM_CPU_Req #(5, FLEN), DM_CPU_Rsp #(FLEN)) hart0_fpr_mem_server;
|
||||
`endif
|
||||
|
||||
// CSR access
|
||||
interface Server #(DM_CPU_Req #(12, XLEN), DM_CPU_Rsp #(XLEN)) hart0_csr_mem_server;
|
||||
interface AXI4_Slave_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) debug_module_mem_server;
|
||||
|
||||
interface AXI4_Slave_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) debug_module_mem_server;
|
||||
// Non-standard
|
||||
interface Put #(Bit #(4)) hart0_put_other_req;
|
||||
`endif
|
||||
|
||||
endinterface
|
||||
|
||||
@@ -206,7 +206,7 @@ module mkCoreW (CoreW_IFC #(N_External_Interrupt_Sources));
|
||||
`ifdef INCLUDE_GDB_CONTROL
|
||||
`ifndef EXTERNAL_DEBUG_MODULE
|
||||
// DM to CPU connections for run-control and other misc requests
|
||||
mkConnection (debug_module.hart0_client_run_halt, proc.hart0_server_run_halt);
|
||||
mkConnection (debug_module.hart0_client_run_halt, proc.hart0_run_halt_server);
|
||||
mkConnection (debug_module.hart0_get_other_req, proc.hart0_put_other_req);
|
||||
`endif
|
||||
`endif
|
||||
@@ -230,8 +230,8 @@ module mkCoreW (CoreW_IFC #(N_External_Interrupt_Sources));
|
||||
rg_fromhost_addr);
|
||||
endrule
|
||||
|
||||
rule rl_hart0_server_run_halt;
|
||||
let tmp <- proc.hart0_server_run_halt.response.get;
|
||||
rule rl_hart0_run_halt_server;
|
||||
let tmp <- proc.hart0_run_halt_server.response.get;
|
||||
endrule
|
||||
|
||||
Reg#(Bool) hart0_halt <- mkReg(False);
|
||||
@@ -409,10 +409,6 @@ module mkCoreW (CoreW_IFC #(N_External_Interrupt_Sources));
|
||||
// Slaves on the local 2x3 fabric
|
||||
// default slave is taken out directly to the Core interface
|
||||
mkConnection (fabric_2x3.v_to_slaves [plic_slave_num], plic.axi4_slave);
|
||||
|
||||
// TODO: This slave can be connected to mkLLCDmaConnect for Debug Module System Bus Access
|
||||
// AXI4_Slave_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) dummy_slave = dummy_AXI4_Slave_ifc;
|
||||
// mkConnection (fabric_2x3.v_to_slaves [near_mem_io_slave_num], dummy_slave);
|
||||
mkConnection (fabric_2x3.v_to_slaves [near_mem_io_slave_num], proc.debug_module_mem_server);
|
||||
|
||||
// ================================================================
|
||||
|
||||
@@ -90,7 +90,7 @@ interface RenameStage;
|
||||
interface Get#(RenameStuck) renameCorrectPathStuck;
|
||||
|
||||
`ifdef INCLUDE_GDB_CONTROL
|
||||
method Action debug_halt;
|
||||
method Action debug_halt_req;
|
||||
method Action debug_resume;
|
||||
`endif
|
||||
endinterface
|
||||
@@ -1105,9 +1105,9 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
|
||||
endmethod
|
||||
|
||||
`ifdef INCLUDE_GDB_CONTROL
|
||||
method Action debug_halt () if (rg_m_halt_req == tagged Invalid);
|
||||
method Action debug_halt_req () if (rg_m_halt_req == tagged Invalid);
|
||||
rg_m_halt_req <= tagged Valid DebugHalt;
|
||||
$display ("%0d: %m.renameStage.renameStage.debug_halt", cur_cycle);
|
||||
$display ("%0d: %m.renameStage.renameStage.debug_halt_req", cur_cycle);
|
||||
endmethod
|
||||
|
||||
method Action debug_resume () if (rg_m_halt_req != tagged Invalid);
|
||||
|
||||
Reference in New Issue
Block a user