Fixes so it now passes ISA test rv64uc-v-rvc ('C' extension, virtual mem). Details below.
Modified:
src_Core/CPU/CsrFile.bsv
Modified method 'trap' to use 'addr' for trap_val (MTVAL) instead of PC
for InstAccessFault and InstPageFault
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
Added 'tval' field to Fetch2Fetch3; set the value on TLB faults; send it out in 'FromFetchStage' struct
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
In rule doRenamingTrap, pass tval from FromFetchStage struct to ToReorderBuffer struct
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
Add 'tval' Ehr to reorderbuffer slot, to accompany 'trap' Ehr.
In method write_enq, store tval from ToReorderBuffer arg into tval Ehr.
In method read_deq, send 'tval' Ehr value into 'ToReorderBuffer' output (goes to CommitStage)
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
Modified rule doCommitTrap_flush to take tval from 'ToReorderBuffer' input from ROB,
for InstAccessFault and InstPageFault
LICENSE
README.md
Clarified licensing of MIT code and Bluespec code
Tests/Run_regression.py
Emptied out 'exclude_list'
builds/RV64ADFIMSU_Toooba_verilator/Makefile
Added 'C' to Makefile
This commit is contained in:
15
LICENSE
15
LICENSE
@@ -1,3 +1,18 @@
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This repository contains code with two licenses.
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1. See: src_Core/RISCY_OOO/LICENSE_RISCY-OOO
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The code in src_Core/RISCY_OOO is mostly a copy of MIT's
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'riscy-ooo' processor, free and open-source under
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LICENSE_RISC-OOO.
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That code has been slightly modified by Bluespec, Inc. (see README for details).
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2. Bluespec's modifications in src_Core/RISCY_OOO and the rest of this
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repository are licensed under the license shown below.
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>================================================================
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Apache License
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Version 2.0, January 2004
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http://www.apache.org/licenses/
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