5d69e3b178
Modified:
src_Core/CPU/CsrFile.bsv
Modified method 'trap' to use 'addr' for trap_val (MTVAL) instead of PC
for InstAccessFault and InstPageFault
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
Added 'tval' field to Fetch2Fetch3; set the value on TLB faults; send it out in 'FromFetchStage' struct
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
In rule doRenamingTrap, pass tval from FromFetchStage struct to ToReorderBuffer struct
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
Add 'tval' Ehr to reorderbuffer slot, to accompany 'trap' Ehr.
In method write_enq, store tval from ToReorderBuffer arg into tval Ehr.
In method read_deq, send 'tval' Ehr value into 'ToReorderBuffer' output (goes to CommitStage)
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
Modified rule doCommitTrap_flush to take tval from 'ToReorderBuffer' input from ROB,
for InstAccessFault and InstPageFault
LICENSE
README.md
Clarified licensing of MIT code and Bluespec code
Tests/Run_regression.py
Emptied out 'exclude_list'
builds/RV64ADFIMSU_Toooba_verilator/Makefile
Added 'C' to Makefile
Open-source RISC-V CPUs from Bluespec, Inc.
***** UNDER CONSTRUCTION *****
***** PLEASE COME BACK LATER (EARLY APRIL 2019) *****
This is one of a family of free, open-source RISC-V CPUs created by Bluespec, Inc.
-
Piccolo: 3-stage, in-order pipeline
Piccolo is intended for low-end applications (Embedded Systems, IoT, microcontrollers, etc.).
-
Flute: 5-stage, in-order pipeline
Flute is intended for low-end to medium applications that require 64-bit operation, an MMU (Virtual Memory) and more performance than Piccolo-class processors.
-
Tooba: superscalar, out-of-order pipeline, slight variation on MIT's RISCY-OOO [In progress!]
Note re. distribution of MIT RISCY-OOO sources.
The directory src_Core/RISCY_OOO contains sources copied from MIT's
riscy-OOO repository. See LICENSE_RISCY-OOO for MIT's license.
[Note: MIT's repository is on an MIT git server, which can only be accessed with credentials; hence the local copy in of these files.]
Bluespec's modifications to files in src_Core/RISCY_OOO are relatively small and mostly additive:
- To add the RISC-V 'C' extension (compressed instructions)
- To add support for Bluespec's Tandem Verification
- To add support for Bluespec's Debug Module.
Building and running Tooba
You will need:
-
A Bluespec tools installation (so you can run 'bsc', the Bluespec compiler for BSV). We recommend version 2018.10.beta1 or later.
-
A Verilator installation. We recommend version 3.922 or later.
Then:
$ cd builds/RV64ADFIMSU_Tuba_verilator
$ make all
This will compile BSV sources using the 'bsc' compiler into Verilog in
the directory Verilog_RTL, then compile and link into a verilator
executable exe_HW_sim.
Then:
$ make test (1)
$ make TEST=<isa_test_name> test (2)
$ make isa_tests (3)
(1) Will run a single ISA test, rv64ui-p-add.
(2) Will do the same, but with the ISA test whose name you supply.
(3) Will run ISA tests for RV64G.