Cheri-research/Toooba
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Fixes so it now passes ISA test rv64uc-v-rvc ('C' extension, virtual mem). Details below.

Browse Source 
Modified:
    src_Core/CPU/CsrFile.bsv
        Modified method 'trap' to use 'addr' for trap_val (MTVAL) instead of PC
	    for InstAccessFault and InstPageFault
    src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
        Added 'tval' field to Fetch2Fetch3; set the value on TLB faults; send it out in 'FromFetchStage' struct
    src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
        In rule doRenamingTrap, pass tval from FromFetchStage struct to ToReorderBuffer struct
    src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
        Add 'tval' Ehr to reorderbuffer slot, to accompany 'trap' Ehr.
	In method write_enq, store tval from ToReorderBuffer arg into tval Ehr.
	In method read_deq, send 'tval' Ehr value into 'ToReorderBuffer' output (goes to CommitStage)
    src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
        Modified rule doCommitTrap_flush to take tval from 'ToReorderBuffer' input from ROB,
            for InstAccessFault and InstPageFault

    LICENSE
    README.md
        Clarified licensing of MIT code and Bluespec code

    Tests/Run_regression.py
        Emptied out 'exclude_list'

    builds/RV64ADFIMSU_Toooba_verilator/Makefile
        Added 'C' to Makefile
This commit is contained in:
rsnikhil
2019-04-10 10:27:40 -04:00
parent 20c87b4c88
commit 5d69e3b178
15 changed files with 42636 additions and 41550 deletions
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6
src_Core/CPU/CsrFile.bsv
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@@ -671,11 +671,13 @@ module mkCsrFile #(Data hartid)(CsrFile);
tagged Exception .e: begin
cause_code = pack(e);
trap_val = (case(e)
InstAddrMisaligned, InstAccessFault,
Breakpoint, InstPageFault: return pc;
InstAddrMisaligned, Breakpoint: return pc;
InstAccessFault, InstPageFault,
LoadAddrMisaligned, LoadAccessFault,
StoreAddrMisaligned, StoreAccessFault,
LoadPageFault, StorePageFault: return addr;
default: return 0;
endcase);
end