Partially bring back tval

We need this to determine which 16b parcel of a 32b instruction caused
the fault (omitting this caused rv64uc-v-rvc to fail).

src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv

@@ -647,11 +647,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
 
         // record trap info
         Addr vaddr = 0;
-        if (   (trap == tagged Exception excInstAccessFault)
-            || (trap == tagged Exception excInstPageFault)) begin
-            vaddr = getAddr(x.pc);
-        end
-        else if(x.ppc_vaddr_csrData matches tagged VAddr .va) begin
+        if(x.ppc_vaddr_csrData matches tagged VAddr .va) begin
             vaddr = va;
         end
         let commitTrap_val = Valid (CommitTrap {

src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv

@@ -166,6 +166,7 @@ typedef struct {
     CapMem pred_next_pc;
     Bool mispred_first_half;
     Maybe#(Exception) cause;
+    Addr tval;                 // in case of exception
     Bool decode_epoch;
     Epoch main_epoch;
 } Fetch3ToDecode deriving(Bits, Eq, FShow);
@@ -190,6 +191,7 @@ typedef struct {
   Bit #(32) orig_inst;    // original 16b or 32b instruction ([1:0] will distinguish 16b or 32b)
   ArchRegs regs;
   Maybe#(Exception) cause;
+  Addr              tval;    // in case of exception
 `ifdef RVFI_DII
   Dii_Id diid;
 `endif
@@ -793,6 +795,7 @@ module mkFetchStage(FetchStage);
                     pred_next_pc: pred_next_pc,
                     mispred_first_half: mispred_first_half,
                     cause: fetch3In.cause,
+                    tval: getAddr(fetch3In.pc),
                     decode_epoch: fetch3In.decode_epoch,
                     main_epoch: fetch3In.main_epoch
                 };
@@ -841,6 +844,7 @@ module mkFetchStage(FetchStage);
                         pred_next_pc: out.pred_next_pc,
                         mispred_first_half: False,
                         cause: tagged Invalid,
+                        tval: 0,
                         decode_epoch: out.decode_epoch,
                         main_epoch: out.main_epoch
                     };
@@ -913,6 +917,7 @@ module mkFetchStage(FetchStage);
                   cause: decodeIn.cause
                   };
                let cause = in.cause;
+               Addr tval = decodeIn.tval;
                if (verbose)
                   $display("Decode: %0d in = ", i, fshow (in));
 
@@ -1026,7 +1031,8 @@ module mkFetchStage(FetchStage);
                                            dInst: dInst,
                                            orig_inst: inst_data[i].orig_inst,
                                            regs: decode_result.regs,
-                                           cause: cause
+                                           cause: cause,
+                                           tval: tval
 `ifdef RVFI_DII
                                            , diid: fromMaybe(?,ids[i])
 `endif

src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv

@@ -337,6 +337,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
         let dInst = x.dInst;
         let arch_regs = x.regs;
         let cause = x.cause;
+        let tval = x.tval;
 
         if(verbose) $display("[doRenaming] trap: ", fshow(x));
 
@@ -360,7 +361,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
                                 claimed_phy_reg: False, // no renaming is done
                                 trap: firstTrap,
                                 // default values of FullResult
-                                ppc_vaddr_csrData: PPC (cast(pc)), // default use PPC
+                                ppc_vaddr_csrData: VAddr (tval),
                                 fflags: 0,
                                 ////////
                                 will_dirty_fpu_state: False,