Cheri-research/Toooba
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Merge remote-tracking branch 'karlis/CHERI' into ks980-prefetch

Browse Source
This commit is contained in:
Jonathan Woodruff
2023-03-30 18:29:21 +00:00
parent 7112be8a46 1ad1dfad6a
commit 60e0e0ad5b
3 changed files with 12 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
builds/Resources/Include_RISCY_Config.mk
View File

@@ -48,7 +48,7 @@ RENAME_DEBUG ?= false
INSTR_PREFETCHER_LOCATION ?= NONE
INSTR_PREFETCHER_TYPE ?= SINGLE_WINDOW
DATA_PREFETCHER_LOCATION ?= L1
DATA_PREFETCHER_TYPE ?= STRIDE
DATA_PREFETCHER_TYPE ?= MARKOV_ON_HIT
# clk frequency depends on core size
ifneq (,$(filter $(CORE_SIZE),TINY SMALL BOOM MEDIUM))

11
src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
View File

@@ -197,6 +197,9 @@ module mkL1Bank#(
Count#(Bit#(64)) currentFullCacheCycles <- mkCount(0);
Reg#(Bit#(64)) lastReportedFullCacheCycles <- mkReg(0);
Count#(Bit#(64)) sentPrefetchReq <- mkCount(0);
Reg#(Bit#(64)) lastReportedSentPrefetchReq <- mkReg(0);
// security flush
`ifdef SECURITY_CACHES
Reg#(Bool) flushDone <- mkReg(True);
@@ -276,6 +279,9 @@ action
`endif
`ifdef PERFORMANCE_MONITORING
EventsL1D events = unpack (0);
events.evt_ST_MISS = saturating_truncate(sentPrefetchReq - lastReportedSentPrefetchReq);
lastReportedSentPrefetchReq <= sentPrefetchReq;
$display("Reporting sent prefetch req: %d", events.evt_ST_MISS);
case(op)
Ld: begin
events.evt_LD_MISS_LAT = saturating_truncate(lat);
@@ -283,7 +289,7 @@ action
end
St: begin
events.evt_ST_MISS_LAT = saturating_truncate(lat);
events.evt_ST_MISS = 1;
//events.evt_ST_MISS = 1;
end
Lr, Sc, Amo: begin
events.evt_AMO_MISS_LAT = saturating_truncate(lat);
@@ -384,8 +390,9 @@ endfunction
(* descending_urgency = "pRsTransfer, cRqTransfer_retry, cRqTransfer_new, createPrefetchRq" *)
(* descending_urgency = "pRqTransfer, cRqTransfer_retry, cRqTransfer_new, createPrefetchRq" *)
rule createPrefetchRq(flushDone);
rule createPrefetchRq(flushDone && addedCRqs - removedCRqs < 6);
Addr addr <- prefetcher.getNextPrefetchAddr;
sentPrefetchReq.incr(1);
procRqT r = ProcRq {
id: ?, //Or maybe do 0 here
addr: addr,

4
src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
View File

@@ -774,14 +774,14 @@ endmodule
module mkBRAMMarkovOnHitPrefetcher(Prefetcher) provisos
(
NumAlias#(maxChainLength, 1),
NumAlias#(maxChainLength, 2),
NumAlias#(numLastRequests, 32),
Alias#(chainLengthT, Bit#(TLog#(TAdd#(maxChainLength,1))))
);
Reg#(LineAddr) lastLastChildRequest <- mkReg(0);
Reg#(LineAddr) lastChildRequest <- mkReg(0);
Reg#(Vector#(numLastRequests, Bit#(32))) lastAddrRequests <- mkReg(replicate(0));
TargetTableBRAM#(65536, 4096) targetTable <- mkTargetTableBRAM;
TargetTableBRAM#(2048, 128) targetTable <- mkTargetTableBRAM;
FIFOF#(LineAddr) targetTableReadResp <- mkBypassFIFOF;
// Stores how many prefetches we can still do in the current chain