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Count sent prefetch requests as Store misses, cache full cycles as stores

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This commit is contained in:
Karlis Susters
2023-03-30 13:06:12 +01:00
parent 06651f1a31
commit 625dbb3066
1 changed files with 9 additions and 2 deletions
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11
src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
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@@ -197,6 +197,9 @@ module mkL1Bank#(
Count#(Bit#(64)) currentFullCacheCycles <- mkCount(0);
Reg#(Bit#(64)) lastReportedFullCacheCycles <- mkReg(0);
Count#(Bit#(64)) sentPrefetchReq <- mkCount(0);
Reg#(Bit#(64)) lastReportedSentPrefetchReq <- mkReg(0);
// security flush
`ifdef SECURITY_CACHES
Reg#(Bool) flushDone <- mkReg(True);
@@ -276,6 +279,9 @@ action
`endif
`ifdef PERFORMANCE_MONITORING
EventsL1D events = unpack (0);
events.evt_ST_MISS = saturating_truncate(sentPrefetchReq - lastReportedSentPrefetchReq);
lastReportedSentPrefetchReq <= sentPrefetchReq;
$display("Reporting sent prefetch req: %d", events.evt_ST_MISS);
case(op)
Ld: begin
events.evt_LD_MISS_LAT = saturating_truncate(lat);
@@ -283,7 +289,7 @@ action
end
St: begin
events.evt_ST_MISS_LAT = saturating_truncate(lat);
events.evt_ST_MISS = 1;
//events.evt_ST_MISS = 1;
end
Lr, Sc, Amo: begin
events.evt_AMO_MISS_LAT = saturating_truncate(lat);
@@ -384,8 +390,9 @@ endfunction
(* descending_urgency = "pRsTransfer, cRqTransfer_retry, cRqTransfer_new, createPrefetchRq" *)
(* descending_urgency = "pRqTransfer, cRqTransfer_retry, cRqTransfer_new, createPrefetchRq" *)
rule createPrefetchRq(flushDone);
rule createPrefetchRq(flushDone && addedCRqs - removedCRqs < 6);
Addr addr <- prefetcher.getNextPrefetchAddr;
sentPrefetchReq.incr(1);
procRqT r = ProcRq {
id: ?, //Or maybe do 0 here
addr: addr,