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saving traces for baremode

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This commit is contained in:
Akilan Selvacoumar
2026-02-05 18:53:37 +00:00
parent bf7bd16c53
commit 656cb4d5e8
6 changed files with 245 additions and 1974 deletions
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11
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
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@@ -531,7 +531,14 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
if(x.regs.src1 matches tagged Valid .src1 &&& src1 != 0) begin
rVal1 <- readRFBypass(src1, regsReady.src1, inIfc.rf_rd1(src1), bypassWire);
end
if (x.ddc_offset) rVal1 = setAddr(ddc, getAddr(rVal1)).value;
if (x.ddc_offset) begin
$display("calling set address");
rVal1 = setAddr(ddc, getAddr(rVal1)).value;
end
else begin
$display("no called set address");
end
$display("outside if and else");
// get rVal2 (check bypass)
CapPipe rVal2 = nullCap;
@@ -598,6 +605,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
endrule
rule doExeMem;
$display("do exe");
regToExeQ.deq;
let regToExe = regToExeQ.first;
let x = regToExe.data;
@@ -650,6 +658,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
endrule
rule doFinishMem;
$display("do finish mem");
// trollToExeQ.deq;
// let regToExe = trollToExeQ.first;
// let lol = regToExe.data;

1
src_Core/RISCY_OOO/procs/lib/DTlb.bsv
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@@ -562,6 +562,7 @@ module mkDTlb#(
// bare mode
pendWait[idx] <= None;
pendResp[idx] <= tuple3(r.addr, Invalid, True);
$display("bare mode");
if(verbose) $display("DTLB %m req (bare): ", fshow(r));
end