adding current changes

Tests/isa/CheriPage.S

@@ -0,0 +1,129 @@
+.option norvc
+.option norelax
+
+# ==================================================
+# Text section
+# ==================================================
+.section .text
+.globl _start
+_start:
+
+vm_boot:
+    # Only hart 0 runs
+    csrr    a0, mhartid
+    bnez    a0, hang
+
+    # --------------------------------------------------
+    # root_pt[0] -> l1_pt
+    # --------------------------------------------------
+    cllc    c0, l1_pt
+    li      t2, 4096
+    csetbounds c0, c0, t2
+
+    cgetaddr t0, c0
+    srli    t0, t0, 12
+    slli    t0, t0, 10
+    ori     t0, t0, 0x1      # V bit
+
+    cllc    c1, root_pt
+    li      t2, 4096
+    csetbounds c1, c1, t2
+    sd      t0, 0(c1)
+
+    # --------------------------------------------------
+    # l1_pt[0] -> l0_pt
+    # --------------------------------------------------
+    cllc    c0, l0_pt
+    li      t2, 4096
+    csetbounds c0, c0, t2
+
+    cgetaddr t0, c0
+    srli    t0, t0, 12
+    slli    t0, t0, 10
+    ori     t0, t0, 0x1      # V bit
+
+    cllc    c1, l1_pt
+    li      t2, 4096
+    csetbounds c1, c1, t2
+    sd      t0, 0(c1)
+
+    # --------------------------------------------------
+    # l0_pt[0] -> leaf (RWX)
+    # --------------------------------------------------
+    li      t0, (1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<6)  # V R W X A
+
+    cllc    c1, l0_pt
+    li      t2, 4096
+    csetbounds c1, c1, t2
+    sd      t0, 0(c1)
+
+    # --------------------------------------------------
+    # Enable Sv39 paging
+    # --------------------------------------------------
+    cllc    c0, root_pt
+    li      t2, 4096
+    csetbounds c0, c0, t2
+
+    cgetaddr t0, c0
+    srli    t0, t0, 12
+    li      t1, (8 << 60)      # MODE = Sv39
+    or      t0, t0, t1
+    csrw    satp, t0
+    sfence.vma zero, zero
+
+    # --------------------------------------------------
+    # Safe data access
+    # --------------------------------------------------
+    cllc    c2, test_buf
+    li      t2, 16
+    csetbounds c2, c2, t2
+
+    li      t3, 0x1122334455667788
+    sd      t3, 0(c2)
+    ld      t4, 0(c2)
+    bne     t3, t4, hang
+
+    # --------------------------------------------------
+    # Signal success
+    # --------------------------------------------------
+    cllc    c0, tohost
+    li      t2, 8
+    csetbounds c0, c0, t2
+    li      t1, 1
+    sd      t1, 0(c0)
+
+hang:
+    wfi
+    j hang
+
+# ==================================================
+# Data section (aligned, contiguous, no .org)
+# ==================================================
+.section .data
+.align 12
+.globl root_pt
+root_pt:
+    .zero 4096      # Root page table
+
+.align 12
+.globl l1_pt
+l1_pt:
+    .zero 4096      # Level 1 page table
+
+.align 12
+.globl l0_pt
+l0_pt:
+    .zero 4096      # Level 0 page table
+
+.align 3
+.globl test_buf
+test_buf:
+    .zero 16        # Test buffer
+
+.globl tohost
+tohost:
+    .dword 0
+
+.globl fromhost
+fromhost:
+    .dword 0

Tests/isa/PageRead.S

@@ -0,0 +1,230 @@
+.option norvc
+.option norelax
+
+# ==================================================
+# Text section
+# ==================================================
+.section .text
+.globl _start
+.globl vm_boot
+
+_start:
+vm_boot:
+    # --------------------------------------------------
+    # Only hart 0 runs
+    # --------------------------------------------------
+    csrr    a0, mhartid
+    bnez    a0, hang
+
+    # --------------------------------------------------
+    # Build page tables
+    # --------------------------------------------------
+
+#
+# Page table setup (Sv39) — binary + hex example
+#
+# Purpose:
+#   Build a VALID page table entry (PTE) in the root page table
+#   that points to the next-level page table (l1_pt).
+#
+# Assume:
+#   l1_pt physical address =
+#     binary: 00000000 10000000 01000000 00110000 00000000
+#     hex:    0x0000000080403000
+#     (page aligned, lower 12 bits = 0)
+#
+# Step-by-step instruction meaning:
+#
+#   la   t0, l1_pt
+#        Load physical address of l1_pt.
+#
+#        t0 =
+#          binary: 00000000 10000000 01000000 00110000 00000000
+#          hex:    0x0000000080403000
+#
+#   srli t0, t0, 12
+#        Drop 12-bit page offset → extract Physical Page Number (PPN).
+#
+#        t0 (PPN) =
+#          binary: 00000000 00000000 10000000 01000000 0011
+#          hex:    0x0000000000080403
+#
+#   slli t0, t0, 10
+#        Shift PPN into PTE bit positions [63:10].
+#        Bits [9:0] are flags.
+#
+#        t0 =
+#          binary: 00000000 00000000 10000000 01000000 0011 0000000000
+#          hex:    0x0000000020100C00
+#
+#   ori  t0, t0, 1
+#        Set bit 0 (V = Valid).
+#
+#        t0 (final PTE) =
+#          binary: 00000000 00000000 10000000 01000000 0011 0000000001
+#          hex:    0x0000000020100C01
+#
+# Memory effect:
+#
+#   root_pt[0] =
+#     bit index:
+#       63                              10 9        0
+#     +----------------------------------+----------+
+#     |   PPN = 0x0000000000080403       | V = 1    |
+#     +----------------------------------+----------+
+#
+#     binary: 00000000 00000000 10000000 01000000 0011 0000000001
+#     hex:    0x0000000020100C01
+#
+# Result:
+#   Root page table entry 0 is VALID and points to l1_pt.
+#   The MMU uses this entry to continue the Sv39 page-table walk.
+#
+
+
+    # root_pt[0] -> l1_pt
+    la      t0, l1_pt
+    srli    t0, t0, 12          # PPN
+    slli    t0, t0, 10          # PTE format
+    ori     t0, t0, 0x1         # V
+    la      t1, root_pt
+    sd      t0, 0(t1)
+
+    # l1_pt[0] -> l0_pt
+    la      t0, l0_pt
+    srli    t0, t0, 12  
+    slli    t0, t0, 10
+    ori     t0, t0, 0x1         # V
+    la      t1, l1_pt
+    sd      t0, 0(t1)
+
+    # l0_pt[0] -> identity mapping (RWX)
+    li      t0, (1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<6)  # V R W X A
+    la      t1, l0_pt
+    sd      t0, 0(t1)
+
+    # --------------------------------------------------
+    # Enable Sv39 paging
+    # --------------------------------------------------
+
+# Enable virtual memory (Sv39) — SATP setup diagram (binary)
+#
+# Assume:
+#   root_pt physical address =
+#     00000000 10000000 01000000 00010000 00000000
+#     (4 KB aligned, lower 12 bits = 0)
+#
+# Instruction flow:
+#
+#   la   t0, root_pt
+#        t0 =
+#        00000000 10000000 01000000 00010000 00000000
+#
+#   srli t0, t0, 12            ; extract PPN
+#        t0 (PPN) =
+#        00000000 00000000 10000000 01000000 0001
+#
+#   li   t1, (8 << 60)         ; MODE = Sv39
+#        t1 =
+#        1000 0000000000000000000000000000000000000000000000000000
+#        ^^^^
+#        MODE[63:60] = 1000 (Sv39)
+#
+#   or   t0, t0, t1
+#        satp value =
+#        1000 0000000000000000000000000000000010000000010000000001
+#        |<-- MODE -->|<----------- ASID ---------->|<---- PPN ---->|
+#
+#   csrw satp, t0
+#        satp register loaded:
+#
+#        63   60 59                              44 43             0
+#        +------+----------------------------------+----------------+
+#        |1000  |0000000000000000                  |0000000010000000010000000001|
+#        +------+----------------------------------+----------------+
+#         MODE=Sv39        ASID=0                     root_pt PPN
+#
+#   sfence.vma zero, zero
+#        Flush all TLB entries so new page tables are used
+#
+# Meaning:
+#   - Virtual memory enabled in Sv39 mode
+#   - Root page table base = root_pt
+#   - ASID = 0
+#   - MMU now performs 3-level page table walks
+#
+
+    la      t0, root_pt
+    srli    t0, t0, 12
+    li      t1, (8 << 60)       # MODE=Sv39
+    or      t0, t0, t1
+    csrw    satp, t0
+    sfence.vma zero, zero
+
+    # --------------------------------------------------
+    # Write data to memory (safe area)
+    # --------------------------------------------------
+    la      t2, test_buf
+    li      t3, 0x1122334455667788
+    sd      t3, 0(t2)
+
+    # --------------------------------------------------
+    # Read data back
+    # --------------------------------------------------
+    ld      t4, 0(t2)
+
+    # Optional check (simple)
+    bne     t3, t4, hang
+
+    # --------------------------------------------------
+    # Signal success
+    # --------------------------------------------------
+    la      t0, tohost
+    li      t1, 1
+    sd      t1, 0(t0)
+
+hang:
+    wfi
+    j hang
+
+# ==================================================
+# Required test symbol
+# ==================================================
+.globl exit
+exit:
+    j exit
+
+# ==================================================
+# Data section
+# ==================================================
+.section .data
+.align 3
+
+.globl tohost
+.globl fromhost
+tohost:
+    .dword 0
+fromhost:
+    .dword 0
+
+# --------------------------------------------------
+# Test buffer (safe data memory)
+# --------------------------------------------------
+.align 3
+test_buf:
+    .zero 16
+
+# --------------------------------------------------
+# Page tables (must be 4 KiB each)
+# --------------------------------------------------
+.align 12
+root_pt:
+    .zero 4096
+
+.align 12
+l1_pt:
+    .zero 4096
+
+.align 12
+l0_pt:
+    .zero 4096

Tests/isa/PageTableTest.S

@@ -12,7 +12,7 @@ _start:
 vm_boot:
     # Only hart 0
     csrr    a0, mhartid
-    bnez    a0, hang
+    bnez    a0, hang.   
 
     # --------------------------------------------------
     # Build page table entries

builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile

@@ -10,8 +10,9 @@ BSC_COMPILATION_FLAGS += -verbose
 
 # TEST ?= rv64ui-p-add
 # TEST ?= rv64um-v-mulw
-TEST ?= Page
+# TEST ?= Page
 # TEST ?= PageReadWrite
+TEST ?= CheriPage
 
 #================================================================
 # Parameter settings for MIT RISCY, setup paths etc. for Include_Common

src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv

@@ -320,6 +320,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
     // pipeline fifos
     let dispToRegQ <- mkMemDispToRegFifo;
     let regToExeQ <- mkMemRegToExeFifo;
+    // let trollToExeQ <- mkMemRegToExeFifo;
 
     // wire to recv bypass
     Vector#(TMul#(2, AluExeNum), RWire#(Tuple2#(PhyRIndx, CapPipe))) bypassWire <- replicateM(mkRWire);
@@ -600,6 +601,8 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
         regToExeQ.deq;
         let regToExe = regToExeQ.first;
         let x = regToExe.data;
+        // trollToExeQ.enq(regToExe);
+        // ==============================
         if(verbose) $display("%t : [doExeMem] ", $time, fshow(regToExe));
 
         let shiftBE = DataMemAccess(x.shiftBEData);
@@ -647,10 +650,18 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
     endrule
 
     rule doFinishMem;
+        // trollToExeQ.deq;
+        // let regToExe = trollToExeQ.first;
+        // let lol = regToExe.data;
+        // =============================
         dTlb.deqProcResp;
         let dTlbResp = dTlb.procResp;
-        let x = dTlbResp.inst;
+        let x = dTlbResp.inst;  
         let {paddr, expCause, allowCapPTE} = dTlbResp.resp;
+        // paddr = getAddr(lol.vaddr);
+        // expCause = False;
+        // allowCapPTE = True;
+
         Maybe#(Trap) cause = Invalid;
         if (expCause matches tagged Valid .c) cause = Valid(Exception(c));
 
@@ -754,6 +765,11 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
         $display("KONATAS\t%0d\t%0d\t0\tMem4", cur_cycle, x.u_id);
         $fflush;
 `endif
+        // Try me! 
+        // if (x.mem_func == St) begin
+        //       paddr = 256;
+        // end
+
         // update LSQ
         LSQUpdateAddrResult updRes <- lsq.updateAddr(
             x.ldstq_tag, cause, x.allowCapLoad && allowCapPTE, paddr, isMMIO, x.shiftedBE

src_Core/RISCY_OOO/procs/lib/DTlb.bsv

@@ -144,7 +144,7 @@ typedef union tagged {
 module mkDTlb#(
     function TlbReq getTlbReq(instT inst)
 )(DTlb::DTlb#(instT)) provisos(Bits#(instT, a__));
-    Bool verbose = False;
+    Bool verbose = True;
 
     // TLB array
     DTlbArray tlb <- mkDTlbArray;