Cheri-research/Toooba
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saving traces for baremode

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This commit is contained in:
Akilan Selvacoumar
2026-02-05 18:53:37 +00:00
parent bf7bd16c53
commit 656cb4d5e8
6 changed files with 245 additions and 1974 deletions
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1
.gitignore vendored
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@@ -23,3 +23,4 @@ src_SSITH_P3/Verilog_RTL_sim
**/TagTableStructure.bsv **/TagTableStructure.bsv
**/GenerateHPMVector.bsv **/GenerateHPMVector.bsv
**/StatCounters.bsv **/StatCounters.bsv
test.txt

4
builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile
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@@ -11,8 +11,8 @@ BSC_COMPILATION_FLAGS += -verbose
# TEST ?= rv64ui-p-add # TEST ?= rv64ui-p-add
# TEST ?= rv64um-v-mulw # TEST ?= rv64um-v-mulw
# TEST ?= Page # TEST ?= Page
# TEST ?= PageReadWrite TEST ?= PageReadWrite
TEST ?= CheriPage # TEST ?= CheriPage
#================================================================ #================================================================
# Parameter settings for MIT RISCY, setup paths etc. for Include_Common # Parameter settings for MIT RISCY, setup paths etc. for Include_Common

2190
builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt
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File diff suppressed because it is too large Load Diff

11
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
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@@ -531,7 +531,14 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
if(x.regs.src1 matches tagged Valid .src1 &&& src1 != 0) begin if(x.regs.src1 matches tagged Valid .src1 &&& src1 != 0) begin
rVal1 <- readRFBypass(src1, regsReady.src1, inIfc.rf_rd1(src1), bypassWire); rVal1 <- readRFBypass(src1, regsReady.src1, inIfc.rf_rd1(src1), bypassWire);
end end
if (x.ddc_offset) rVal1 = setAddr(ddc, getAddr(rVal1)).value; if (x.ddc_offset) begin
$display("calling set address");
rVal1 = setAddr(ddc, getAddr(rVal1)).value;
end
else begin
$display("no called set address");
end
$display("outside if and else");
// get rVal2 (check bypass) // get rVal2 (check bypass)
CapPipe rVal2 = nullCap; CapPipe rVal2 = nullCap;
@@ -598,6 +605,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
endrule endrule
rule doExeMem; rule doExeMem;
$display("do exe");
regToExeQ.deq; regToExeQ.deq;
let regToExe = regToExeQ.first; let regToExe = regToExeQ.first;
let x = regToExe.data; let x = regToExe.data;
@@ -650,6 +658,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
endrule endrule
rule doFinishMem; rule doFinishMem;
$display("do finish mem");
// trollToExeQ.deq; // trollToExeQ.deq;
// let regToExe = trollToExeQ.first; // let regToExe = trollToExeQ.first;
// let lol = regToExe.data; // let lol = regToExe.data;

1
src_Core/RISCY_OOO/procs/lib/DTlb.bsv
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@@ -562,6 +562,7 @@ module mkDTlb#(
// bare mode // bare mode
pendWait[idx] <= None; pendWait[idx] <= None;
pendResp[idx] <= tuple3(r.addr, Invalid, True); pendResp[idx] <= tuple3(r.addr, Invalid, True);
$display("bare mode");
if(verbose) $display("DTLB %m req (bare): ", fshow(r)); if(verbose) $display("DTLB %m req (bare): ", fshow(r));
end end

12
test.txt
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@@ -1,12 +0,0 @@
Let me know if this message works well on behalf of all of us.
Hi Jan,
This is a very small gesture from Jose, Mathews, Yukang and Akilan. We have transferred 200 pounds equally contributed by all of us. As you are moving in and settling into your new place, we hope this can help you and Samantha cover certain expenses like buying furniture or for your very efficient interrail travel pass in the near future.
We will definetely miss the german embassy in Slatefort. Happy new year in advance from all of us!
Regards,
Jose, Mathews, Yukang and Akilan
(Your UK representation of transportation
reform)