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Provide opt-in wedge debugging info

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When DEBUG_WEDGE is defined, expose the last committed and next in the
reorder buffer PC and corresponding instruction via DMI registers, since
even when the core is wedged and we can't read GPRs etc we can still
interact with the debug module itself. Hopefully this proves useful for
debugging wedges.
This commit is contained in:
Jessica Clarke
2020-07-07 23:59:35 +01:00
parent 40f8109263
commit 68d3bd484e
10 changed files with 174 additions and 2 deletions
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61
src_Core/Debug_Module/Debug_Module.bsv
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@@ -91,6 +91,12 @@ import DM_Run_Control :: *;
import DM_Abstract_Commands :: *;
import DM_System_Bus :: *;
`ifdef DEBUG_WEDGE
import ConfigReg :: *;
import CHERICap :: *;
import CHERICC_Fat :: *;
`endif
// ================================================================
export DM_Common :: *;
@@ -126,6 +132,15 @@ interface Debug_Module_IFC;
// CSR access
interface Client #(DM_CPU_Req #(12, XLEN), DM_CPU_Rsp #(XLEN)) hart0_csr_mem_client;
// Optional debug from commit stage and ROB
`ifdef DEBUG_WEDGE
(* always_enabled *)
method Action hart0_last_inst (Tuple2 #(CapMem, Bit #(32)) pcc_inst);
(* always_enabled *)
method Action hart0_next_inst (Tuple2 #(CapMem, Bit #(32)) pcc_inst);
`endif
// ----------------
// Facing Platform
@@ -154,6 +169,13 @@ module mkDebug_Module (Debug_Module_IFC);
FIFO#(DM_Addr) f_read_addr <- mkFIFO1;
`ifdef DEBUG_WEDGE
Reg #(CapMem) rg_last_pcc <- mkConfigReg (unpack (0));
Reg #(Bit #(32)) rg_last_inst <- mkConfigReg (0);
Reg #(CapMem) rg_next_pcc <- mkConfigReg (unpack (0));
Reg #(Bit #(32)) rg_next_inst <- mkConfigReg (0);
`endif
// ================================================================
// Reset all three parts when dm_run_control.dmactive is low
@@ -228,6 +250,32 @@ module mkDebug_Module (Debug_Module_IFC);
dm_word <- dm_system_bus.av_read (dm_addr);
`ifdef DEBUG_WEDGE
else if (dm_addr == dm_addr_custom0)
dm_word = getAddr (rg_last_pcc) [31:0];
else if (dm_addr == dm_addr_custom1)
dm_word = getAddr (rg_last_pcc) [63:32];
else if (dm_addr == dm_addr_custom2)
dm_word = rg_last_inst;
else if (dm_addr == dm_addr_custom3)
dm_word = getAddr (rg_next_pcc) [31:0];
else if (dm_addr == dm_addr_custom4)
dm_word = getAddr (rg_next_pcc) [63:32];
else if (dm_addr == dm_addr_custom5)
dm_word = rg_next_inst;
`endif
else begin
// TODO: set error status?
dm_word = 0;
@@ -315,6 +363,19 @@ module mkDebug_Module (Debug_Module_IFC);
// CSR access
interface Client hart0_csr_mem_client = dm_abstract_commands.hart0_csr_mem_client;
// Optional debug from commit stage
`ifdef DEBUG_WEDGE
method Action hart0_last_inst (Tuple2 #(CapMem, Bit #(32)) pcc_inst);
rg_last_pcc <= tpl_1 (pcc_inst);
rg_last_inst <= tpl_2 (pcc_inst);
endmethod
method Action hart0_next_inst (Tuple2 #(CapMem, Bit #(32)) pcc_inst);
rg_next_pcc <= tpl_1 (pcc_inst);
rg_next_inst <= tpl_2 (pcc_inst);
endmethod
`endif
// ----------------
// Facing Platform