Update to AXI lite for debug module port
This commit is contained in:
gameboo
committed by
Alexandre Joannou
Alexandre Joannou
parent
b9ee27f390
commit
72320b32b2
@@ -60,7 +60,8 @@ import Cur_Cycle :: *;
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import GetPut_Aux :: *;
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import Routable :: *;
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import AXI4 :: *;
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import AXI4_Utils :: *;
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import AXI4Lite :: *;
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import SourceSink :: *;
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import TagControllerAXI :: *;
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import CacheCore :: *;
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@@ -118,15 +119,18 @@ typedef WindCoreMid #( // AXI manager 0 port parameters
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// AXI subordinate 0 port parameters
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, 0, 0, 0, 0, 0, 0, 0, 0
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// Number of interrupt lines
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, N_External_Interrupt_Sources) WindCoreMidIfc;
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, t_n_irq) CoreW_IFC #(numeric type t_n_irq);
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//(* synthesize *)
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module mkCoreW (WindCoreMidIfc);
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Reset dfltRst <- exposeCurrentReset;
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Reset otherRst = ?;
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match {.fromDbgReset, .ifc} <- mkCoreResetHelper ( dfltRst
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, reset_by otherRst );
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otherRst <- mkResetEither (dfltRst, fromDbgReset);
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module mkCoreW (CoreW_IFC #(t_n_irq));
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Clock clk <- exposeCurrentClock;
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Reset rst <- exposeCurrentReset;
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let newRst <- mkReset (0, True, clk, reset_by rst);
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match {.otherRst, .ifc} <- mkCoreResetHelper ( rst
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, reset_by newRst.new_rst);
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rule rl_forward_debug_reset (otherRst);
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newRst.assertReset;
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endrule
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return ifc;
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endmodule
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@@ -134,7 +138,7 @@ endmodule
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// hacks to the nicer outer interface, and not have to use a large amount of
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// reset_by to decouple the debug module from the rest...
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module mkCoreResetHelper #(Reset toDbgReset)
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(Tuple2#(Reset, WindCoreMidIfc));
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(Tuple2#(PulseWire, CoreW_IFC #(t_n_irq)));
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// ================================================================
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// Notes on 'reset'
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@@ -447,36 +451,36 @@ module mkCoreResetHelper #(Reset toDbgReset)
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// ================================================================
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// Connect external debug module interface
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let f_dbg_reqs <- mkFIFO1;
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let f_dbg_rsps <- mkFIFO1;
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let dbgShim <- mkAXI4LiteShim (reset_by toDbgReset);
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rule rl_debug_module_req;
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case (f_dbg_reqs.first) matches
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tagged ReadReq {.rd_addr}: debug_module.dmi.read_addr (rd_addr);
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tagged WriteReq {.wr_addr, .wr_data}:
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debug_module.dmi.write (wr_addr, wr_data);
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endcase
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f_dbg_reqs.deq;
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rule rl_debug_module_read_req;
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let arFlit <- get (dbgShim.master.ar);
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debug_module.dmi.read_addr (arFlit.araddr);
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endrule
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rule rl_debug_module_rsp;
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rule rl_debug_module_read_rsp;
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let x <- debug_module.dmi.read_data;
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f_dbg_rsps.enq (ReadRsp(x));
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dbgShim.master.r.put(AXI4Lite_RFlit { rdata: x, rresp: OKAY, ruser: ?});
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endrule
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rule rl_debug_module_write_req;
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let awFlit <- get (dbgShim.master.aw);
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let wFlit <- get (dbgShim.master.w);
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dbgShim.master.b.put(defaultValue);
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debug_module.dmi.write (awFlit.awaddr, wFlit.wdata);
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endrule
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let fromDbgReset <- mkReset (0, False, clk);
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let fromDbgReset <- mkPulseWire (reset_by toDbgReset);
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rule rl_debug_module_send_reset;
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let _ <- debug_module.ndm_reset_client.request.get;
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fromDbgReset.assertReset;
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fromDbgReset.send;
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endrule
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// ================================================================
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// Connect external interrupts to the PLIC and Proc
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Vector #(N_External_Interrupt_Sources, Reg #(Bool)) irq_reg
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Vector #(t_n_irq, Reg #(Bool)) irq_reg
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<- replicateM (mkReg (False));
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Vector #(N_External_Interrupt_Sources, Put #(Bool)) irq_ifc;
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for (Integer i = 0; i < valueof (N_External_Interrupt_Sources); i = i + 1) begin
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Vector #(t_n_irq, Put #(Bool)) irq_ifc;
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for (Integer i = 0; i < valueof (t_n_irq); i = i + 1) begin
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irq_ifc [i] = interface Put;
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method put = writeReg (irq_reg[i]);
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endinterface;
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@@ -523,10 +527,10 @@ module mkCoreResetHelper #(Reset toDbgReset)
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// ================================================================
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// INTERFACE
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let ifc = interface WindCoreMidIfc;
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let ifc = interface CoreW_IFC;
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// debug related signals
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// ---------------------
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interface debugModuleServer = toGPServer (f_dbg_reqs, f_dbg_rsps);
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interface debug_subordinate = dbgShim.slave;
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// interrupt related signals
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// -------------------------
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@@ -566,7 +570,7 @@ module mkCoreResetHelper #(Reset toDbgReset)
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`endif
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*/
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return tuple2 (fromDbgReset.new_rst, ifc);
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return tuple2 (fromDbgReset, ifc);
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endmodule: mkCoreResetHelper
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// ================================================================
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@@ -1,204 +0,0 @@
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// Copyright (c) 2018-2020 Bluespec, Inc. All Rights Reserved.
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//
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//-
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// RVFI_DII + CHERI modifications:
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// Copyright (c) 2020 Alexandre Joannou
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// Copyright (c) 2020 Peter Rugg
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// Copyright (c) 2020 Jonathan Woodruff
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// All rights reserved.
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//
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// This software was developed by SRI International and the University of
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// Cambridge Computer Laboratory (Department of Computer Science and
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// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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// DARPA SSITH research programme.
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//
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// This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet").
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//-
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package CoreW_IFC;
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// ================================================================
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// This package defines the interface of a CoreW module which
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// contains:
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// - mkProc (the RISC-V CPU; this a variant of MIT's RISCY-OOO mkProc)
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// Note: MIT's RISCY-OOO internally has a 'mkCore' and hence this
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// interface and its module is called 'CoreW', to disambiguate.
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// - mkFabric_2x3
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// - mkNear_Mem_IO_AXI4
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// - mkPLIC_16_CoreNumX2_7
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// - mkTV_Encode (Tandem-Verification logic, optional: INCLUDE_TANDEM_VERIF)
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// - mkDebug_Module (RISC-V Debug Module, optional: INCLUDE_GDB_CONTROL)
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// ================================================================
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// BSV library imports
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import Vector :: *;
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import GetPut :: *;
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import ClientServer :: *;
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// ----------------
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// BSV additional libs
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import AXI4 :: *;
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// ================================================================
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// Project imports
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// Main fabric
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import Fabric_Defs :: *;
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// External interrupt request interface
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import PLIC :: *;
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`ifdef INCLUDE_GDB_CONTROL
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import Debug_Module :: *;
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`endif
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`ifdef RVFI_DII
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import ProcTypes :: *;
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`endif
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`ifdef INCLUDE_TANDEM_VERIF
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import ProcTypes :: *;
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import Trace_Data2 :: *;
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import TV_Info :: *;
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`endif
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// ================================================================
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// The CoreW interface
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interface CoreW_IFC #(numeric type t_n_interrupt_sources);
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// ----------------------------------------------------------------
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// Debugging: set core's verbosity
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method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay);
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// ----------------------------------------------------------------
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// Start
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method Action start (Bool is_running, Bit #(64) tohost_addr, Bit #(64) fromhost_addr);
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// ----------------------------------------------------------------
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// AXI4 Fabric interfaces
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// CPU IMem to Fabric master interface
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interface AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
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0, 0, 0, 0, 0) cpu_imem_master;
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// CPU DMem to Fabric master interface
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interface AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
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0, 0, 0, 0, 0) cpu_dmem_master;
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// ----------------------------------------------------------------
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// External interrupt sources
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interface Vector #(t_n_interrupt_sources, PLIC_Source_IFC) core_external_interrupt_sources;
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// ----------------------------------------------------------------
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// Non-maskable interrupt request
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(* always_ready, always_enabled *)
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method Action nmi_req (Bool set_not_clear);
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`ifdef RVFI_DII
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interface Toooba_RVFI_DII_Server rvfi_dii_server;
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`endif
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`ifdef INCLUDE_GDB_CONTROL
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// ----------------------------------------------------------------
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// Optional Debug Module interfaces
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// ----------------
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// DMI (Debug Module Interface) facing remote debugger
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interface DMI dmi;
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// ----------------
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// Facing Platform
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// Non-Debug-Module Reset (reset all except DM)
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interface Client #(Bool, Bool) ndm_reset_client;
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`endif
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`ifdef INCLUDE_TANDEM_VERIF
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// ----------------------------------------------------------------
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// Optional Tandem Verifier interface output tuples (n,vb),
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// where 'vb' is a vector of bytes
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// with relevant bytes in locations [0]..[n-1]
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interface Get #(Info_CPU_to_Verifier) tv_verifier_info_get;
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`endif
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endinterface
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// ================================================================
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// The Synthesizable CoreW interface (same with Synth AXI)
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interface CoreW_IFC_Synth #(numeric type t_n_interrupt_sources);
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// ----------------------------------------------------------------
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// Debugging: set core's verbosity
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method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay);
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// ----------------------------------------------------------------
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// Start
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method Action start (Bool is_running, Bit #(64) tohost_addr, Bit #(64) fromhost_addr);
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// ----------------------------------------------------------------
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// AXI4 Fabric interfaces
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// CPU IMem to Fabric master interface
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interface AXI4_Master_Sig #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
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0, 0, 0, 0, 0) cpu_imem_master;
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// CPU DMem to Fabric master interface
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interface AXI4_Master_Sig #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
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0, 0, 0, 0, 0) cpu_dmem_master;
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// ----------------------------------------------------------------
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// External interrupt sources
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interface Vector #(t_n_interrupt_sources, PLIC_Source_IFC) core_external_interrupt_sources;
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// ----------------------------------------------------------------
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// Non-maskable interrupt request
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(* always_ready, always_enabled *)
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method Action nmi_req (Bool set_not_clear);
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`ifdef RVFI_DII
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interface Toooba_RVFI_DII_Server rvfi_dii_server;
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`endif
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`ifdef INCLUDE_GDB_CONTROL
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// ----------------------------------------------------------------
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// Optional Debug Module interfaces
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// ----------------
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// DMI (Debug Module Interface) facing remote debugger
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interface DMI dmi;
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// ----------------
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// Facing Platform
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// Non-Debug-Module Reset (reset all except DM)
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interface Client #(Bool, Bool) ndm_reset_client;
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`endif
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`ifdef INCLUDE_TANDEM_VERIF
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// ----------------------------------------------------------------
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// Optional Tandem Verifier interface output tuples (n,vb),
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// where 'vb' is a vector of bytes
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// with relevant bytes in locations [0]..[n-1]
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interface Get #(Info_CPU_to_Verifier) tv_verifier_info_get;
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`endif
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endinterface
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// ================================================================
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endpackage
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