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Changes needed for working TagController in Toooba.

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This commit is contained in:
jon
2020-06-02 19:05:56 +01:00
parent 4cd611ce30
commit 7612738ff5
3 changed files with 31 additions and 37 deletions
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28
src_Core/Core/CoreW.bsv
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@@ -147,13 +147,19 @@ module mkCoreW #(Reset dm_power_on_reset)
// RISCY-OOO processor
// TODO (when we do multicore): need resets for each core.
Proc_IFC proc <- mkProc (reset_by hart0_reset);
// handle imem interface
let tmp0 <- fromAXI4_Master_Synth(proc.master0);
let tmp1 <- toUnguarded_AXI4_Master(tmp0);
let proc_imem = toAXI4_Master_Synth(extendIDFields(zeroMasterUserFields(tmp1), 0));
// handle uncached interface
let tmp0 <- fromAXI4_Master_Synth(proc.master1, reset_by hart0_reset);
let proc_uncached = toAXI4_Master_Synth(extendIDFields(zeroMasterUserFields(tmp0), 0));
// Bridge for uncached expernal bus transactions.
let uncached_mem_shim <- mkAXI4ShimFF(reset_by hart0_reset);
let ug_uncached_mem_shim_master <- toUnguarded_AXI4_Master(zeroMasterUserFields(extendIDFields(uncached_mem_shim.master,0)), reset_by hart0_reset);
// handle cached interface
// AXI4 tagController
let tagController <- mkTagControllerAXI(reset_by hart0_reset); // TODO double check if reseting like this is good enough
AXI4_Master#(5, 64, 64, 0, 1, 0, 0, 1) tmp2 <- fromAXI4_Master_Synth(proc.master0, reset_by hart0_reset);
mkConnection(tmp2, tagController.slave, reset_by hart0_reset);
// PLIC (Platform-Level Interrupt Controller)
PLIC_IFC_16_2_7 plic <- mkPLIC_16_2_7;
@@ -334,7 +340,7 @@ module mkCoreW #(Reset dm_power_on_reset)
Wd_AR_User, Wd_R_User))
master_vector = newVector;
//let master_vector = newVector;
master_vector[cpu_dmem_master_num] = proc.master1;
master_vector[cpu_uncached_master_num] = proc_uncached;
master_vector[debug_module_sba_master_num] = dm_master_local;
// Slaves on the local 2x3 fabric
@@ -345,7 +351,7 @@ module mkCoreW #(Reset dm_power_on_reset)
Wd_AR_User, Wd_R_User))
slave_vector = newVector;
//let slave_vector = newVector;
slave_vector[default_slave_num] = toAXI4_Slave_Synth(tagController.slave);
slave_vector[default_slave_num] = toAXI4_Slave_Synth(uncached_mem_shim.slave);
slave_vector[llc_slave_num] = proc.debug_module_mem_server;
slave_vector[plic_slave_num] = plic.axi4_slave;
@@ -411,11 +417,11 @@ module mkCoreW #(Reset dm_power_on_reset)
// ----------------------------------------------------------------
// AXI4 Fabric interfaces
// IMem to Fabric master interface
interface cpu_imem_master = proc_imem;
// Cached master to Fabric master interface
interface cpu_imem_master = toAXI4_Master_Synth(tagController.master);
// DMem to Fabric master interface
interface cpu_dmem_master = toAXI4_Master_Synth(tagController.master);
// Uncached master to Fabric master interface
interface cpu_dmem_master = toAXI4_Master_Synth(ug_uncached_mem_shim_master);
// ----------------------------------------------------------------
// External interrupt sources
@@ -471,7 +477,7 @@ endmodule: mkCoreW
// ----------------
// Fabric port numbers for masters
Master_Num_2x3 cpu_dmem_master_num = 0;
Master_Num_2x3 cpu_uncached_master_num = 0;
Master_Num_2x3 debug_module_sba_master_num = 1;
// ----------------

16
src_Testbench/SoC/SoC_Map.bsv
View File

@@ -64,24 +64,12 @@ typedef struct {
deriving (FShow);
SoC_Map_Struct soc_map_struct =
`ifndef RVFI_DII
SoC_Map_Struct {
near_mem_io_addr_base: 'h_0200_0000,
main_mem_addr_base: 'h_8000_0000,
main_mem_addr_size: 'h_1000_0000,
pc_reset_value: 'h_0000_1000
};
`else
SoC_Map_Struct {
near_mem_io_addr_base: 'h_0200_0000,
main_mem_addr_base: 'h_8000_0000,
main_mem_addr_size: 'h_0080_0000,
main_mem_addr_size: 'h_4000_0000,
pc_reset_value: 'h_8000_0000
};
`endif
// ================================================================
// Interface and module for the address map
@@ -150,7 +138,7 @@ module mkSoC_Map (SoC_Map_IFC);
let mem0_controller_addr_range = Range {
base: 'h_8000_0000,
size: 'h_1000_0000 // 256 MB
size: 'h_4000_0000 // 1 GB
};
// ----------------------------------------------------------------

24
src_Testbench/Top/Mem_Model.bsv
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@@ -51,16 +51,15 @@ endinterface
typedef 'h4000_0000 Bytes_Per_Mem;
`ifdef RVFI_DII
typedef 'h0000_0000 Zeroed_0_start;
typedef RVFI_DII_Mem_Size Zeroed_0_end;
typedef 'h0080_0000 Zeroed_0_end;
typedef 'h3f00_0000 Zeroed_1_start;
typedef 'h3fff_ff00 Zeroed_1_end;
typedef TLog#(TDiv#(Bits_per_Raw_Mem_Word,8)) ByteOffsetInWord;
typedef 8192 ZeroMemWidth;
typedef TLog#(ZeroMemWidth) LogZMWidth;
Integer wordOffsetWidth = valueOf(ByteOffsetInWord);
Integer lineInZeroesOffsetWidth = valueOf(LogZMWidth) + valueOf(ByteOffsetInWord);
typedef Bit#(TSub#(TLog#(TSub#(Zeroed_0_end, Zeroed_0_start)), TAdd#(LogZMWidth,ByteOffsetInWord))) Offset_Zeroes_0;
typedef Bit#(TSub#(TLog#(TSub#(Zeroed_1_end, Zeroed_1_start)), TAdd#(LogZMWidth,ByteOffsetInWord))) Offset_Zeroes_1;
typedef 'h3f00_0000 Zeroed_1_start;
typedef 'h3fff_ff00 Zeroed_1_end;
Integer lineInZeroesOffsetWidth = valueOf(LogZMWidth);
typedef Bit#(TSub#(TSub#(TLog#(TSub#(Zeroed_0_end, Zeroed_0_start)), LogZMWidth), ByteOffsetInWord)) Offset_Zeroes_0;
typedef Bit#(TSub#(TSub#(TLog#(TSub#(Zeroed_1_end, Zeroed_1_start)), LogZMWidth), ByteOffsetInWord)) Offset_Zeroes_1;
`endif
// ================================================================
@@ -69,7 +68,7 @@ typedef 'h3fff_ff00 Zeroed_1_end;
(* synthesize *)
module mkMem_Model (Mem_Model_IFC);
Integer verbosity = 0; // 0 = quiet; 1 = verbose
Integer verbosity = 1; // 0 = quiet; 1 = verbose
Raw_Mem_Addr alloc_size = fromInteger(valueOf(TDiv#(TMul#(Bytes_Per_Mem,8), Bits_per_Raw_Mem_Word))); //(raw mem words)
@@ -89,9 +88,9 @@ module mkMem_Model (Mem_Model_IFC);
Reg#(Offset_Zeroes_1) reset_count_1 <- mkReg(~0);
rule doZeroesReset(!reset_done);
zeroes_0.upd(reset_count_0, 0);
reset_count_0 <= reset_count_0 - 1;
zeroes_1.upd(reset_count_1, 0);
reset_count_1 <= reset_count_1 - 1;
if (reset_count_0 != 0) reset_count_0 <= reset_count_0 - 1;
if (reset_count_1 != 0) reset_count_1 <= reset_count_1 - 1;
if (reset_count_0 == 0 && reset_count_1 == 0) reset_done <= True;
endrule
`else
@@ -108,7 +107,7 @@ module mkMem_Model (Mem_Model_IFC);
interface Put request;
method Action put (MemoryRequest #(Bits_per_Raw_Mem_Addr, Bits_per_Raw_Mem_Word) req) if (reset_done);
`ifdef RVFI_DII
Bit#(LogZMWidth) offsetLo = truncate((req.address - zeroed_0_start)>>wordOffsetWidth);
Bit#(LogZMWidth) offsetLo = truncate((req.address - zeroed_0_start));
Offset_Zeroes_0 word0 = truncate((req.address - zeroed_0_start)>>lineInZeroesOffsetWidth);
Bit#(ZeroMemWidth) zeroes_0_word = zeroes_0.sub(word0);
Offset_Zeroes_1 word1 = truncate((req.address - zeroed_1_start)>>lineInZeroesOffsetWidth);
@@ -137,7 +136,8 @@ module mkMem_Model (Mem_Model_IFC);
else begin
let x = rf.sub (req.address);
`ifdef RVFI_DII
$display("req addr: ", fshow(req.address), ", zeroed_0_start: ", fshow(zeroed_0_start), ", zeroed_1_start: ", fshow(zeroed_1_start));
$display("req addr: ", fshow(req.address), ", zeroed_0_start: ", fshow(zeroed_0_start), "-", fshow(zeroed_0_end),
", zeroed_1_start: ", fshow(zeroed_1_start), "-", fshow(zeroed_1_end));
if (req.address < zeroed_0_end && req.address >= zeroed_0_start && zeroes_0.sub(word0)[offsetLo] == 0) x = 0;
if (req.address < zeroed_1_end && req.address >= zeroed_1_start && zeroes_1.sub(word1)[offsetLo] == 0) x = 0;
`endif