Set up config for an L2 next-2-line-on-miss instruction prefetcher

builds/Resources/Include_RISCY_Config.mk

@@ -45,9 +45,9 @@ SIM_LLC_ARBITER_LAT ?=
 # default check cache deadlock and rename error
 CHECK_DEADLOCK ?= true
 RENAME_DEBUG ?= false
-INSTR_PREFETCHER_LOCATION ?= NONE
+INSTR_PREFETCHER_LOCATION ?= LL
 INSTR_PREFETCHER_TYPE ?= NEXT_LINE_ON_MISS
-DATA_PREFETCHER_LOCATION ?= L1
+DATA_PREFETCHER_LOCATION ?= NONE
 DATA_PREFETCHER_TYPE ?= BLOCK
 
 # clk frequency depends on core size