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Increase the capacity of f32d to enable full throughput.

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I don't know why this is necessary, but this allows performance parity
with the baseline.
This commit is contained in:
jon
2020-08-11 15:30:03 +01:00
parent 9230fcc3b4
commit 7a93056b8b
1 changed files with 1 additions and 1 deletions
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src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
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@@ -343,7 +343,7 @@ module mkFetchStage(FetchStage);
// Pipeline Stage FIFOs
Fifo#(2, Tuple2#(Bit#(TLog#(SupSizeX2)),Fetch1ToFetch2)) f12f2 <- mkCFFifo;
Fifo#(4, Tuple2#(Bit#(TLog#(SupSizeX2)),Fetch2ToFetch3)) f22f3 <- mkCFFifo; // FIFO should match I$ latency
SupFifo#(SupSizeX2, 2, Fetch3ToDecode) f32d <- mkSupFifo;
SupFifo#(SupSizeX2, 3, Fetch3ToDecode) f32d <- mkSupFifo; // This fifo needs a capacity of 3 for full throughput. Unknown why.
SupFifo#(SupSize, 2, FromFetchStage) out_fifo <- mkSupFifo;
// Can the fifo size be smaller?