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Repurpose L1D store miss count to track number of cycles cache is full

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This commit is contained in:
Karlis Susters
2023-03-24 15:11:08 +00:00
parent a4ad28d865
commit 7d7d38ad49
1 changed files with 24 additions and 1 deletions
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25
src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
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@@ -191,6 +191,12 @@ module mkL1Bank#(
let prefetcher <- mkL1DPrefetcher;
let llcPrefetcher <- mkLLDPrefetcherInL1D;
Count#(Bit#(8)) addedCRqs <- mkCount(0);
Count#(Bit#(8)) removedCRqs <- mkCount(0);
Count#(Bit#(64)) currentFullCacheCycles <- mkCount(0);
Reg#(Bit#(64)) lastReportedFullCacheCycles <- mkReg(0);
// security flush
`ifdef SECURITY_CACHES
Reg#(Bool) flushDone <- mkReg(True);
@@ -233,6 +239,9 @@ action
`endif
`ifdef PERFORMANCE_MONITORING
EventsL1D events = unpack (0);
events.evt_ST_MISS = saturating_truncate(currentFullCacheCycles - lastReportedFullCacheCycles);
lastReportedFullCacheCycles <= currentFullCacheCycles;
$display("Reporting full cache cycles: %d", events.evt_ST_MISS);
case(op)
Ld: events.evt_LD = 1;
St: events.evt_ST = 1;
@@ -274,7 +283,7 @@ action
end
St: begin
events.evt_ST_MISS_LAT = saturating_truncate(lat);
events.evt_ST_MISS = 1;
//events.evt_ST_MISS = 1;
end
Lr, Sc, Amo: begin
events.evt_AMO_MISS_LAT = saturating_truncate(lat);
@@ -305,6 +314,7 @@ endfunction
mshrIdx: n
}));
cRqIsPrefetch[n] <= False;
addedCRqs.incr(1);
if (verbose)
$display("%t L1 %m cRqTransfer_retry: ", $time,
fshow(n), " ; ",
@@ -318,6 +328,7 @@ endfunction
rule cRqTransfer_new(!cRqRetryIndexQ.notEmpty && flushDone);
procRqT r <- toGet(rqFromCQ).get;
cRqIdxT n <- cRqMshr.cRqTransfer.getEmptyEntryInit(r);
addedCRqs.incr(1);
// send to pipeline
pipeline.send(CRq (L1PipeRqIn {
addr: r.addr,
@@ -363,6 +374,14 @@ endfunction
endrule
rule print_cRqIndexQ_len;
//$display("L1D cRqIndexQ length= %d", addedCRqs-removedCRqs);
endrule
rule incrFullCacheCycles (addedCRqs - removedCRqs == 8);
currentFullCacheCycles.incr(1);
endrule
(* descending_urgency = "pRsTransfer, cRqTransfer_retry, cRqTransfer_new, createPrefetchRq" *)
(* descending_urgency = "pRqTransfer, cRqTransfer_retry, cRqTransfer_new, createPrefetchRq" *)
rule createPrefetchRq(flushDone);
@@ -379,6 +398,7 @@ endfunction
pcHash: ?
};
cRqIdxT n <- cRqMshr.cRqTransfer.getEmptyEntryInit(r);
addedCRqs.incr(1);
// send to pipeline
pipeline.send(CRq (L1PipeRqIn {
addr: r.addr,
@@ -649,6 +669,7 @@ endfunction
);
// release MSHR entry
cRqMshr.pipelineResp.releaseEntry(n);
removedCRqs.incr(1);
end
else begin
processAmo <= Valid (AmoHitInfo {
@@ -711,6 +732,7 @@ endfunction
);
// release MSHR entry
cRqMshr.pipelineResp.releaseEntry(n);
removedCRqs.incr(1);
// reset state
processAmo <= Invalid;
endrule
@@ -752,6 +774,7 @@ endfunction
end
// release MSHR entry
cRqMshr.pipelineResp.releaseEntry(n);
removedCRqs.incr(1);
if (verbose)
$display("%t L1 %m pipelineResp: Sc early fail func: ", $time,
fshow(resetOwner), " ; ",