Introduce the WindCoreInterface
This commit is contained in:
gameboo
committed by
Alexandre Joannou
Alexandre Joannou
parent
8cb96bae5c
commit
812c961360
3
.gitmodules
vendored
3
.gitmodules
vendored
@@ -13,3 +13,6 @@
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[submodule "libs/RISCV_HPM_Events"]
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path = libs/RISCV_HPM_Events
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url = https://github.com/CTSRD-CHERI/RISCV_HPM_Events.git
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[submodule "libs/WindCoreInterface"]
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path = libs/WindCoreInterface
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url = https://github.com/CTSRD-CHERI/WindCoreInterface.git
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@@ -11,6 +11,23 @@ EXTRA_DIRS = $(RISCY_HOME)/../../src_Verifier:$(RISCY_HOME)/../../src_Verifier/B
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# ================================================================
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# RISC-V config macros passed into Bluespec 'bsc' compiler
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BSC_COMPILATION_FLAGS += \
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-D RV64 \
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-D ISA_PRIV_M -D ISA_PRIV_U -D ISA_PRIV_S \
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-D SV39 \
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-D ISA_I -D ISA_M -D ISA_A -D ISA_F -D ISA_D -D ISA_FD_DIV -D ISA_C \
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-D SHIFT_BARREL \
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-D MULT_SYNTH \
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-D Near_Mem_Caches \
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-D FABRIC64 \
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-D CheriBusBytes=8 \
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-D CheriMasterIDWidth=1 \
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-D CheriTransactionIDWidth=5 \
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-D CAP128 -D BLUESIM \
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-D MEM64 \
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-D RISCV \
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-D INCLUDE_GDB_CONTROL
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# Default ISA test
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TEST ?= rv64ui-p-add
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@@ -56,11 +56,13 @@ TESTBENCH_DIRS = $(REPO)/src_Testbench/Top:$(REPO)/src_Testbench/SoC
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BLUESTUFF_DIRS = $(REPO)/libs/BlueStuff:$(REPO)/libs/BlueStuff/AXI:$(REPO)/libs/BlueStuff/BlueUtils:$(REPO)/libs/BlueStuff/BlueBasics
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WINDCOREIFC_DIRS = $(REPO)/libs/WindCoreInterface
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TAGCONTROLLER_DIRS = $(REPO)/libs/TagController/TagController:$(REPO)/libs/TagController/TagController/CacheCore
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RISCV_HPM_Events_DIR = $(REPO)/libs/RISCV_HPM_Events
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BSC_PATH = $(BLUESTUFF_DIRS):$(ALL_RISCY_DIRS):$(CORE_DIRS):$(TESTBENCH_DIRS):$(TAGCONTROLLER_DIRS):$(RISCV_HPM_Events_DIR):+
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BSC_PATH = $(BLUESTUFF_DIRS):$(WINDCOREIFC_DIRS):$(ALL_RISCY_DIRS):$(CORE_DIRS):$(TESTBENCH_DIRS):$(TAGCONTROLLER_DIRS):$(RISCV_HPM_Events_DIR):+
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# ----------------
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# Top-level file and module
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1
libs/WindCoreInterface
Submodule
1
libs/WindCoreInterface
Submodule
Submodule libs/WindCoreInterface added at dbcabbf45e
@@ -46,6 +46,7 @@ package CoreW;
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// BSV library imports
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import Vector :: *;
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import FIFO :: *;
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import FIFOF :: *;
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import GetPut :: *;
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import ClientServer :: *;
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@@ -84,9 +85,9 @@ import SoC_Map :: *;
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import Debug_Module :: *;
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`endif
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import CoreW_IFC :: *;
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import Proc_IFC :: *;
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import Proc :: *;
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import WindCoreInterface :: *;
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import Proc_IFC :: *;
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import Proc :: *;
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import PLIC :: *;
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import PLIC_16_CoreNumX2_7 :: *;
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@@ -110,9 +111,16 @@ import DM_CPU_Req_Rsp ::*;
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// ================================================================
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// The Core module
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(* synthesize *)
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//(* synthesize *)
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module mkCoreW #(Reset dm_power_on_reset)
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(CoreW_IFC #(N_External_Interrupt_Sources));
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(WindCoreLo #( // AXI manager 0 port parameters
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TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0
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// AXI manager 1 port parameters
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, TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0
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// AXI subordinate 0 port parameters
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, t_s_mid, t_s_addr, t_s_data, 0, 0, 0, 0, 0
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// Number of interrupt lines
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, N_External_Interrupt_Sources));
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// ================================================================
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// Notes on 'reset'
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@@ -201,8 +209,9 @@ module mkCoreW #(Reset dm_power_on_reset)
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PLIC_IFC_16_CoreNumX2_7 plic <- mkPLIC_16_CoreNumX2_7;
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`ifdef INCLUDE_GDB_CONTROL
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let dbg_reset <- mkReset (0, True, clk, reset_by dm_power_on_reset);
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// Debug Module
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Debug_Module_IFC debug_module <- mkDebug_Module (reset_by dm_power_on_reset);
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Debug_Module_IFC debug_module <- mkDebug_Module (reset_by dbg_reset.new_rst);
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`endif
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`ifdef INCLUDE_TANDEM_VERIF
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@@ -423,78 +432,110 @@ module mkCoreW #(Reset dm_power_on_reset)
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endrule
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// ================================================================
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// INTERFACE
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// Connect external debug module interface
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// ----------------------------------------------------------------
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// Debugging: set core's verbosity, htif addrs
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let f_dbg_reqs <- mkFIFO1;
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let f_dbg_rsps <- mkFIFO1;
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let f_dbg_rst_reqs <- mkFIFO1;
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let f_dbg_rst_rsps <- mkFIFO1;
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method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay);
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// Warning: ignoring logdelay
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proc.set_verbosity (verbosity);
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endmethod
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rule rl_debug_module_req;
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case (f_dbg_reqs.first) matches
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tagged ReadReq {.rd_addr}: debug_module.dmi.read_addr (rd_addr);
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tagged WriteReq {.wr_addr, .wr_data}:
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debug_module.dmi.write (wr_addr, wr_data);
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tagged ResetReq: dbg_reset.assertReset;
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endcase
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f_dbg_reqs.deq;
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endrule
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// ----------------------------------------------------------------
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// Start
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rule rl_debug_module_rsp;
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let x <- debug_module.dmi.read_data;
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f_dbg_rsps.enq (ReadRsp(x));
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endrule
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method Action start (Bool is_running, Bit #(64) tohost_addr, Bit #(64) fromhost_addr);
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rule rl_debug_module_reset_req;
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let _ <- debug_module.ndm_reset_client.request.get;
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f_dbg_rst_reqs.enq(?);
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endrule
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rule rl_debug_module_reset_rsp;
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debug_module.ndm_reset_client.response.put(True);
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f_dbg_rst_rsps.deq;
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endrule
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// ================================================================
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// Connect external interrupts to the PLIC and Proc
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Vector #(t_n_irq, SetClear) irq_ifc;
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for (Integer i = 0; i < valueof(t_n_irq); i = i + 1) begin
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irq_ifc [i] = interface SetClear;
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method set = plic.v_sources[i].m_interrupt_req(True);
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method clear = plic.v_sources[i].m_interrupt_req(False);
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endinterface;
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end
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let nmirq_ifc = interface SetClear;
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// TODO: fixup; passing const False for now
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method set = proc.non_maskable_interrupt_req (False);
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method clear = proc.non_maskable_interrupt_req (False);
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endinterface;
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// ================================================================
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// Connect other control and status signals
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let f_ctrl_reqs <- mkFIFO1;
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let f_ctrl_rsps <- mkFIFO1;
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function do_release = action
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plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_range.base),
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zeroExtend (rangeTop(soc_map.m_plic_addr_range)));
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proc.start ( True, soc_map_struct.pc_reset_value, 0, 0);
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//proc.set_verbosity (verbosity);
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endaction;
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let pc = soc_map_struct.pc_reset_value;
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proc.start (is_running, pc, tohost_addr, fromhost_addr);
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rule rl_ctrl_req;
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case (f_ctrl_reqs.first) matches
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tagged ReleaseReq: do_release;
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tagged StatusReq: $display ("StatusReq not supported in Toooba");
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endcase
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f_ctrl_reqs.deq;
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endrule
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`ifdef INCLUDE_GDB_CONTROL
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// Save for potential future use by rl_dm_harts_reset
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rg_tohost_addr <= tohost_addr;
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rg_fromhost_addr <= fromhost_addr;
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`endif
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rule rl_ctrl_rsp;
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f_ctrl_rsps.enq (StatusRsp(?));
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endrule
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$display ("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)",
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cur_cycle, pc, tohost_addr, fromhost_addr);
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endmethod
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// ================================================================
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// INTERFACE
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// ----------------------------------------------------------------
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// AXI4 Fabric interfaces
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// debug related signals
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// ---------------------
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interface debugModuleServer = toGPServer (f_dbg_reqs, f_dbg_rsps);
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interface debugModuleResetClient = toGPClient (f_dbg_rst_reqs, f_dbg_rst_rsps);
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// interrupt related signals
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// -------------------------
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interface irq = irq_ifc;
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interface nmirq = nmirq_ifc;
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// other control and status signals
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// --------------------------------
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interface controlStatusServer = toGPServer (f_ctrl_reqs, f_ctrl_rsps);
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// memory interfaces
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// -----------------
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// Cached master to Fabric master interface
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interface cpu_imem_master = tagController.master;
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interface manager_0 = tagController.master;
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// Uncached master to Fabric master interface
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interface cpu_dmem_master = prepend_AXI4_Master_id(0, zero_AXI4_Master_user(uncached_mem_shim.master));
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// ----------------------------------------------------------------
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// External interrupt sources
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interface core_external_interrupt_sources = plic.v_sources;
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// ----------------------------------------------------------------
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// Non-maskable interrupt request
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method Action nmi_req (Bool set_not_clear);
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// TODO: fixup; passing const False for now
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proc.non_maskable_interrupt_req (False);
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endmethod
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interface manager_1 = extendIDFields(zeroMasterUserFields(uncached_mem_shim.master), 0);
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// TODO:
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interface subordinate_0 = culDeSac;
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/*
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`ifdef RVFI_DII
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interface Toooba_RVFI_DII_Server rvfi_dii_server = proc.rvfi_dii_server;
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`endif
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`ifdef INCLUDE_GDB_CONTROL
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// ----------------------------------------------------------------
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// Optional DM interfaces
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// ----------------
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// DMI (Debug Module Interface) facing remote debugger
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interface DMI dmi = debug_module.dmi;
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// ----------------
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// Facing Platform
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// Non-Debug-Module Reset (reset all except DM)
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interface Client ndm_reset_client = debug_module.ndm_reset_client;
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`endif
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`ifdef INCLUDE_TANDEM_VERIF
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// ----------------------------------------------------------------
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// Optional TV interface
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@@ -506,9 +547,11 @@ module mkCoreW #(Reset dm_power_on_reset)
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endmethod
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endinterface
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`endif
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*/
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endmodule: mkCoreW
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/*
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(* synthesize *)
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module mkCoreW_Synth #(Reset dm_power_on_reset)
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(CoreW_IFC_Synth #(N_External_Interrupt_Sources));
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@@ -533,6 +576,7 @@ module mkCoreW_Synth #(Reset dm_power_on_reset)
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interface tv_verifier_info_get = core.tv_verifier_info_get;
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`endif
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endmodule
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*/
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// ================================================================
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// 2x3 Fabric for this Core
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