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Fixes for Tandem Verification for store-values, CSR values on traps, etc. (detail below)

Browse Source 
src_Core/CPU/CsrFile.bsv
    Various fixes for WARL'd values of mstatus and sstatus, medeleg,
    Added tval field in Trap_Updates returned by csrf.trap

src_Core/Core/Trace_Data2.bsv
    Added fields for store_data and store_data_BE

src_Core/Core/Trace_Data2_to_Trace_Data.bsv
    Added treatment of store_data and store_data_BE
    Fixed bug in next_pc for mkTrace_RET

src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
    Fixed Trace_Data2 struct to TV for pc in case of xRET, and tval in case of trap

src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
    Added store_data and store_data_BE in calls to rob_setExecuted_doFinishMem

src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
    Added store_data and store_data_BE in methods rob_setExecuted_doFinishMem
This commit is contained in:
rsnikhil
2020-02-12 19:43:04 -05:00
parent ddcb784297
commit 8434df2dac
9 changed files with 17552 additions and 16951 deletions
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14308
builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v
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File diff suppressed because it is too large Load Diff

20020
builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkReorderBufferSynth.v
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File diff suppressed because it is too large Load Diff

38
builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkRobRowSynth.v
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@@ -38,6 +38,8 @@
// setExecuted_doFinishFpuMulDiv_0_set_dst_data I 64
// setExecuted_doFinishFpuMulDiv_0_set_fflags I 5
// setExecuted_doFinishMem_vaddr I 64
// setExecuted_doFinishMem_store_data I 64 unused
// setExecuted_doFinishMem_store_data_BE I 8 unused
// setExecuted_doFinishMem_access_at_commit I 1
// setExecuted_doFinishMem_non_mmio_st_done I 1
// dependsOn_wrongSpec_tag I 4
@@ -105,6 +107,8 @@ module mkRobRowSynth(CLK,
RDY_setExecuted_doFinishFpuMulDiv_0_set,
setExecuted_doFinishMem_vaddr,
setExecuted_doFinishMem_store_data,
setExecuted_doFinishMem_store_data_BE,
setExecuted_doFinishMem_access_at_commit,
setExecuted_doFinishMem_non_mmio_st_done,
EN_setExecuted_doFinishMem,
@@ -170,6 +174,8 @@ module mkRobRowSynth(CLK,
// action method setExecuted_doFinishMem
input [63 : 0] setExecuted_doFinishMem_vaddr;
input [63 : 0] setExecuted_doFinishMem_store_data;
input [7 : 0] setExecuted_doFinishMem_store_data_BE;
input setExecuted_doFinishMem_access_at_commit;
input setExecuted_doFinishMem_non_mmio_st_done;
input EN_setExecuted_doFinishMem;
@@ -508,8 +514,8 @@ module mkRobRowSynth(CLK,
IF_m_ppc_vaddr_csrData_lat_3_whas__66_THEN_m_p_ETC___d208,
x__h26961;
wire [11 : 0] IF_m_spec_bits_lat_1_whas__84_THEN_m_spec_bits_ETC___d290,
bs__h33169,
sb__h33204,
bs__h33177,
sb__h33212,
upd__h17993;
wire [4 : 0] IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d153,
x_read_deq_fflags__h26056;
@@ -611,7 +617,7 @@ module mkRobRowSynth(CLK,
assign RDY_getOrig_Inst = 1'd1 ;
// value method dependsOn_wrongSpec
assign dependsOn_wrongSpec = bs__h33169[dependsOn_wrongSpec_tag] ;
assign dependsOn_wrongSpec = bs__h33177[dependsOn_wrongSpec_tag] ;
assign RDY_dependsOn_wrongSpec = 1'd1 ;
// action method correctSpeculation
@@ -1362,7 +1368,7 @@ module mkRobRowSynth(CLK,
!m_ppc_vaddr_csrData_dummy2_1$Q_OUT ||
!m_ppc_vaddr_csrData_dummy2_2$Q_OUT ||
!m_ppc_vaddr_csrData_dummy2_3$Q_OUT ;
assign bs__h33169 =
assign bs__h33177 =
(m_spec_bits_dummy2_0$Q_OUT && m_spec_bits_dummy2_1$Q_OUT &&
m_spec_bits_dummy2_2$Q_OUT) ?
m_spec_bits_rl :
@@ -1394,7 +1400,7 @@ module mkRobRowSynth(CLK,
m_nonMMIOStDone_dummy2_1$Q_OUT &&
m_nonMMIOStDone_rl,
m_epochIncremented,
bs__h33169 } ;
bs__h33177 } ;
assign m_rg_dst_data_62_CONCAT_m_csr_63_BIT_12_64_CON_ETC___d643 =
{ m_rg_dst_data,
m_csr[12],
@@ -1412,11 +1418,11 @@ module mkRobRowSynth(CLK,
m_trap_dummy2_0$Q_OUT && m_trap_dummy2_1$Q_OUT &&
m_trap_dummy2_2$Q_OUT &&
m_trap_rl[5] ;
assign sb__h33204 =
assign sb__h33212 =
m_spec_bits_dummy2_2$Q_OUT ?
IF_m_spec_bits_lat_1_whas__84_THEN_m_spec_bits_ETC___d290 :
12'd0 ;
assign upd__h17993 = sb__h33204 & correctSpeculation_mask ;
assign upd__h17993 = sb__h33212 & correctSpeculation_mask ;
assign x__h26961 =
(m_tval_dummy2_0$Q_OUT && m_tval_dummy2_1$Q_OUT &&
m_tval_dummy2_2$Q_OUT) ?
@@ -1709,7 +1715,7 @@ module mkRobRowSynth(CLK,
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishAlu_0_set &&
NOT_m_csr_63_BIT_12_64_EQ_setExecuted_doFinish_ETC___d685)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 225, column 60\ncsr valid should match");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 236, column 60\ncsr valid should match");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishAlu_0_set &&
NOT_m_csr_63_BIT_12_64_EQ_setExecuted_doFinish_ETC___d685)
@@ -1721,7 +1727,7 @@ module mkRobRowSynth(CLK,
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishAlu_1_set &&
NOT_m_csr_63_BIT_12_64_EQ_setExecuted_doFinish_ETC___d693)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 225, column 60\ncsr valid should match");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 236, column 60\ncsr valid should match");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishAlu_1_set &&
NOT_m_csr_63_BIT_12_64_EQ_setExecuted_doFinish_ETC___d693)
@@ -1733,7 +1739,7 @@ module mkRobRowSynth(CLK,
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_deqLSQ &&
m_trap_dummy2_0_read__41_AND_m_trap_dummy2_1_r_ETC___d546)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 349, column 52\ncannot have trap");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 373, column 52\ncannot have trap");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_deqLSQ &&
m_trap_dummy2_0_read__41_AND_m_trap_dummy2_1_r_ETC___d546)
@@ -1747,7 +1753,7 @@ module mkRobRowSynth(CLK,
if (EN_setExecuted_doFinishMem &&
setExecuted_doFinishMem_access_at_commit &&
setExecuted_doFinishMem_non_mmio_st_done)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 253, column 18\ncannot both be true");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 266, column 18\ncannot both be true");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishMem &&
setExecuted_doFinishMem_access_at_commit &&
@@ -1762,7 +1768,7 @@ module mkRobRowSynth(CLK,
if (EN_setExecuted_doFinishMem &&
setExecuted_doFinishMem_non_mmio_st_done &&
m_iType != 5'd5)
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 257, column 35\nmust be St");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 270, column 35\nmust be St");
if (RST_N != `BSV_RESET_VALUE)
if (EN_setExecuted_doFinishMem &&
setExecuted_doFinishMem_non_mmio_st_done &&
@@ -1773,7 +1779,7 @@ module mkRobRowSynth(CLK,
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[18])
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 310, column 40\nld killed must be false");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 330, column 40\nld killed must be false");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[18]) $finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
@@ -1781,7 +1787,7 @@ module mkRobRowSynth(CLK,
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[15])
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 311, column 48\nmem access at commit must be false");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 331, column 48\nmem access at commit must be false");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[15]) $finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
@@ -1789,7 +1795,7 @@ module mkRobRowSynth(CLK,
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[14])
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 312, column 42\nlsq notified must be false");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 332, column 42\nlsq notified must be false");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[14]) $finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
@@ -1797,7 +1803,7 @@ module mkRobRowSynth(CLK,
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[13])
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 313, column 36\nnon mmio st must be false");
$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv\", line 333, column 36\nnon mmio st must be false");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write_enq && write_enq_x[13]) $finish(32'd0);
end

36
src_Core/CPU/CsrFile.bsv
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@@ -58,6 +58,7 @@ typedef struct {
Data status;
Data cause;
Data epc;
Data tval;
`endif
} Trap_Updates
deriving (Bits, FShow);
@@ -498,7 +499,7 @@ module mkCsrFile #(Data hartid)(CsrFile);
Bit #(1) ie_vec_prvS_val,
Bit #(1) ie_vec_prvU_val);
return {fn_sd_val (xs_val, fs_val),
29'b0, uxl_val, 12'b0,
27'b0, 2'b0, uxl_val, 12'b0,
mxr_val, sum_val, 1'b0, xs_val, fs_val,
4'b0, spp_val,
2'b0,
@@ -782,7 +783,7 @@ module mkCsrFile #(Data hartid)(CsrFile);
x [1], // ie_vec[prvS]
x [0]); // ie_vec[prvU]
CSRmtvec: { x[63:2], 1'b0, x[0]};
CSRmedeleg: { 52'b0, x[11], 1'b0, x[9:8], x[7], 1'b0, x[5:4], x[3], 1'b0, x[1:0]};
CSRmedeleg: { 48'b0, x[15], 1'b0, x[13:12], x[11], 1'b0, x[9:0]};
CSRmideleg: { 52'b0, x[11], 1'b0, x[9:8], x[7], 1'b0, x[5:4], x[3], 1'b0, x[1:0]};
CSRmip: { 52'b0, x[11], 1'b0, x[9:8], x[7], 1'b0, x[5:4], x[3], 1'b0, x[1:0]};
CSRmie: { 52'b0, x[11], 1'b0, x[9:8], x[7], 1'b0, x[5:4], x[3], 1'b0, x[1:0]};
@@ -954,7 +955,8 @@ module mkCsrFile #(Data hartid)(CsrFile);
, prv: prvS,
status: sstatus_val,
cause: scause_val,
epc: pc
epc: pc,
tval: trap_val
`endif
};
end
@@ -988,7 +990,8 @@ module mkCsrFile #(Data hartid)(CsrFile);
, prv: prvM,
status: mstatus_val,
cause: mcause_val,
epc: pc
epc: pc,
tval: trap_val
`endif
};
end
@@ -1027,18 +1030,25 @@ module mkCsrFile #(Data hartid)(CsrFile);
ie_vec[prvS] <= prev_ie_vec[prvS];
prev_ie_vec[prvS] <= 1;
Data sstatus_val = fn_sstatus_val (uxl_reg,
mxr_reg, sum_reg,
xs_reg, fs_reg,
/* spp_reg */ prvU [0],
/* prev_ie_vec_[prvS] */ 1,
prev_ie_vec [prvU],
/* ie_vec [prvS] */ prev_ie_vec[prvS],
ie_vec [prvU]);
// For Tandem Verification, we return the full underlying MSTATUS register
Data mstatus_val = fn_mstatus_val(sxl_reg, uxl_reg,
tsr_reg, tw_reg, tvm_reg,
mxr_reg, sum_reg, mprv_reg,
xs_reg, fs_reg,
mpp_reg,
/* spp_reg */ prvU [0],
prev_ie_vec [prvM],
/* prev_ie_vec_[prvS] */ 1,
prev_ie_vec [prvU],
ie_vec [prvM],
/* ie_vec [prvS] */ prev_ie_vec[prvS],
ie_vec [prvU]);
return RET_Updates {new_pc: sepc_csr
`ifdef INCLUDE_TANDEM_VERIF
, prv: prev_prv_vec[prvS],
status: sstatus_val
status: mstatus_val
`endif
};
endmethod

2
src_Core/Core/Trace_Data2.bsv
View File

@@ -30,6 +30,8 @@ typedef struct {
IType iType;
Maybe#(ArchRIndx) dst; // Invalid, GPR or FPR destination ("Rd")
Data dst_data;
Data store_data; // For mem instrs that store data
ByteEn store_data_BE;
Maybe #(CSR) csr;
Maybe #(Trap) trap;
Addr tval; // in case of trap

17
src_Core/Core/Trace_Data2_to_Trace_Data.bsv
View File

@@ -65,6 +65,11 @@ module mkTrace_Data2_to_Trace_Data (Trace_Data2_to_Trace_Data_IFC);
ISize isize = ((td2.orig_inst [1:0] == 2'b11) ? ISIZE32BIT : ISIZE16BIT);
Addr fall_thru_PC = td2.pc + ((td2.orig_inst [1:0] == 2'b11) ? 4 : 2);
Bit #(3) st_funct3 = (td2.store_data_BE [7] ? 3'b_011 // Doubleword
: (td2.store_data_BE [3] ? 3'b_010 // Word
: (td2.store_data_BE [1] ? 3'b_001 // HalfWord
: 3'b000))); // Byte
Bit #(5) gpr_rd = 0;
if (td2.dst matches tagged Valid (tagged Gpr .r)) gpr_rd = r;
@@ -133,10 +138,10 @@ module mkTrace_Data2_to_Trace_Data (Trace_Data2_to_Trace_Data_IFC);
else if (td2.ppc_vaddr_csrData matches tagged VAddr .eaddr
&&& (td2.iType == St))
td = mkTrace_I_STORE (fall_thru_PC,
?, // TODO: funct3,
st_funct3,
isize,
td2.orig_inst,
?, // store-value
td2.store_data, // rs2_val
eaddr);
else if (td2.ppc_vaddr_csrData matches tagged CSRData .csr_data
@@ -165,7 +170,7 @@ module mkTrace_Data2_to_Trace_Data (Trace_Data2_to_Trace_Data_IFC);
else if ( (td2.iType == Mret)
|| (td2.iType == Sret))
td = mkTrace_RET (fall_thru_PC, isize, td2.orig_inst, td2.prv, td2.status);
td = mkTrace_RET (td2.pc, isize, td2.orig_inst, td2.prv, td2.status);
else if ( (td2.iType == Fence)
|| (td2.iType == FenceI)
@@ -179,12 +184,12 @@ module mkTrace_Data2_to_Trace_Data (Trace_Data2_to_Trace_Data_IFC);
|| (td2.iType == Lr)
|| (td2.iType == Sc)))
td = mkTrace_AMO (fall_thru_PC,
0, // TODO: funct3
st_funct3,
isize,
td2.orig_inst,
gpr_rd,
td2.dst_data, // rd_val
0, // TODO: rs2_val
td2.dst_data, // rd_val
td2.store_data, // rs2_val
eaddr);
else if ( (td2.iType == Unsupported)

16
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
View File

@@ -183,17 +183,21 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
Maybe #(Trap_Updates) m_trap_updates,
Maybe #(RET_Updates) m_ret_updates);
action
CsrFile csrf = inIfc.csrfIfc;
let mstatus = csrf.rd (CSRmstatus);
CsrFile csrf = inIfc.csrfIfc;
let mstatus = csrf.rd (CSRmstatus);
let tval = (m_trap_updates matches tagged Valid .tu ? tu.tval : deq_data.tval);
let upd_pc = (m_ret_updates matches tagged Valid .ru ? ru.new_pc : deq_data.pc);
let x = Trace_Data2 {serial_num: serial_num,
pc: deq_data.pc,
pc: upd_pc,
orig_inst: deq_data.orig_inst,
iType: deq_data.iType,
dst: deq_data.dst,
dst_data: deq_data.dst_data,
store_data: deq_data.store_data,
store_data_BE: deq_data.store_data_BE,
csr: deq_data.csr,
trap: deq_data.trap,
tval: deq_data.tval,
tval: tval,
ppc_vaddr_csrData: deq_data.ppc_vaddr_csrData,
fflags: deq_data.fflags,
will_dirty_fpu_state: deq_data.will_dirty_fpu_state,
@@ -570,7 +574,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
end
`ifdef INCLUDE_GDB_CONTROL
else if (trap.trap == tagged Exception Breakpoint) begin
inIfc.commitCsrInstOrInterrupt;
inIfc.commitCsrInstOrInterrupt; // TODO: Why?
end
`endif
@@ -611,8 +615,6 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
if (! debugger_halt) begin
// trap handling & redirect
// let new_pc <- csrf.trap(trap.trap, trap.pc, trap.addr); // OLD: WITHOUT TV INFO
// inIfc.redirectPc(new_pc); // OLD: WITHOUT TV INFO
let trap_updates <- csrf.trap(trap.trap, trap.pc, trap.addr);
inIfc.redirectPc(trap_updates.new_pc);

27
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
View File

@@ -79,7 +79,12 @@ typedef struct {
LdStQTag ldstq_tag;
// result
ByteEn shiftedBE;
Addr vaddr; // virtual addr
Addr vaddr; // virtual addr
`ifdef INCLUDE_TANDEM_VERIF
// for those mem instrs that store data
Data store_data;
ByteEn store_data_BE;
`endif
Bool misaligned;
} MemExeToFinish deriving(Bits, Eq, FShow);
@@ -146,7 +151,10 @@ interface MemExeInput;
method Data csrf_rd(CSR csr);
// ROB
method Addr rob_getPC(InstTag t);
method Action rob_setExecuted_doFinishMem(InstTag t, Addr vaddr, Bool access_at_commit, Bool non_mmio_st_done);
method Action rob_setExecuted_doFinishMem(InstTag t,
Addr vaddr,
Data store_data, ByteEn store_data_BE,
Bool access_at_commit, Bool non_mmio_st_done);
`ifdef INCLUDE_TANDEM_VERIF
method Action rob_setExecuted_doFinishMem_RegData (InstTag t, Data dst_data);
`endif
@@ -454,6 +462,10 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
ldstq_tag: x.ldstq_tag,
shiftedBE: shiftBE,
vaddr: vaddr,
`ifdef INCLUDE_TANDEM_VERIF
store_data: data,
store_data_BE: origBE,
`endif
misaligned: memAddrMisaligned(vaddr, origBE)
},
specBits: regToExe.spec_bits
@@ -469,6 +481,13 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
if(verbose) $display("[doFinishMem] ", fshow(dTlbResp));
if(isValid(cause) && verbose) $display(" [doFinishMem - dTlb response] PAGEFAULT!");
Data store_data = ?;
ByteEn store_data_BE = ?;
`ifdef INCLUDE_TANDEM_VERIF
store_data = x.store_data;
store_data_BE = x.store_data_BE;
`endif
// check misalignment
if(!isValid(cause) && x.misaligned) begin
case(x.mem_func)
@@ -503,7 +522,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
endcase);
Bool access_at_commit = !isValid(cause) && (isMMIO || isLrScAmo);
Bool non_mmio_st_done = !isValid(cause) && !isMMIO && x.mem_func == St;
inIfc.rob_setExecuted_doFinishMem(x.tag, x.vaddr,
inIfc.rob_setExecuted_doFinishMem(x.tag, x.vaddr, store_data, store_data_BE,
access_at_commit, non_mmio_st_done);
// update LSQ
@@ -511,7 +530,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
x.ldstq_tag, cause, paddr, isMMIO, x.shiftedBE
);
// issue non-MMIO Ld which has no excpetion and is not waiting for
// issue non-MMIO Ld which has no exception and is not waiting for
// wrong path resp
if (x.mem_func == Ld && !isMMIO &&
!isValid(cause) && !updRes.waitWPResp) begin

39
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
View File

@@ -52,6 +52,11 @@ typedef struct {
IType iType;
Maybe#(ArchRIndx) dst; // Invalid, GPR or FPR destination ("Rd")
Data dst_data; // Output of instruction into destination register
`ifdef INCLUDE_TANDEM_VERIF
// Store-data, for those mem instrs that store data
Data store_data;
ByteEn store_data_BE;
`endif
Maybe#(CSR) csr;
Bool claimed_phy_reg; // whether we need to commmit renaming
Maybe#(Trap) trap;
@@ -108,7 +113,9 @@ interface ReorderBufferRowEhr#(numeric type aluExeNum, numeric type fpuMulDivExe
// faulting inst cannot have this set, since there is no access to
// perform), and non-MMIO St can become Executed (NOTE faulting
// instructions are not Executed, they are set at deqLSQ time)
method Action setExecuted_doFinishMem(Addr vaddr, Bool access_at_commit, Bool non_mmio_st_done);
method Action setExecuted_doFinishMem(Addr vaddr,
Data store_data, ByteEn store_data_BE,
Bool access_at_commit, Bool non_mmio_st_done);
`ifdef INCLUDE_TANDEM_VERIF
// Used after a Ld, Lr, Sc, Amo to record reg data
@@ -183,6 +190,10 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
Reg#(IType) iType <- mkRegU;
Reg #(Maybe #(ArchRIndx)) rg_dst_reg <- mkRegU;
Reg #(Data) rg_dst_data <- mkRegU;
`ifdef INCLUDE_TANDEM_VERIF
Reg #(Data) rg_store_data <- mkRegU;
Reg #(ByteEn) rg_store_data_BE <- mkRegU;
`endif
Reg#(Maybe#(CSR)) csr <- mkRegU;
Reg#(Bool) claimed_phy_reg <- mkRegU;
Ehr#(3, Maybe#(Trap)) trap <- mkEhr(?);
@@ -248,7 +259,9 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
interface setExecuted_doFinishFpuMulDiv = fpuMulDivExe;
method Action setExecuted_doFinishMem(Addr vaddr, Bool access_at_commit, Bool non_mmio_st_done);
method Action setExecuted_doFinishMem(Addr vaddr,
Data store_data, ByteEn store_data_BE,
Bool access_at_commit, Bool non_mmio_st_done);
doAssert(!(access_at_commit && non_mmio_st_done),
"cannot both be true");
// update ROB state
@@ -258,6 +271,11 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
end
// update VAddr
ppc_vaddr_csrData[pvc_finishMem_port] <= VAddr (vaddr);
`ifdef INCLUDE_TANDEM_VERIF
// Store-data (for mem instrs that store data)
rg_store_data <= store_data;
rg_store_data_BE <= store_data_BE;
`endif
// update access at commit
memAccessAtCommit[accessCom_finishMem_port] <= access_at_commit;
// udpate non mmio st
@@ -285,6 +303,8 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
iType <= x.iType;
rg_dst_reg <= x.dst;
// rg_dst_data will be written after inst execution
// rg_store_data will be written in Mem pipeline
// rg_store_data_BE will be written in Mem pipeline
csr <= x.csr;
claimed_phy_reg <= x.claimed_phy_reg;
trap[trap_enq_port] <= x.trap;
@@ -320,6 +340,10 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
iType: iType,
dst: rg_dst_reg,
dst_data: rg_dst_data,
`ifdef INCLUDE_TANDEM_VERIF
store_data: rg_store_data,
store_data_BE: rg_store_data_BE,
`endif
csr: csr,
claimed_phy_reg: claimed_phy_reg,
trap: trap[trap_deq_port],
@@ -439,7 +463,10 @@ interface SupReorderBuffer#(numeric type aluExeNum, numeric type fpuMulDivExeNum
interface Vector#(aluExeNum, ROB_setExecuted_doFinishAlu) setExecuted_doFinishAlu;
interface Vector#(fpuMulDivExeNum, ROB_setExecuted_doFinishFpuMulDiv) setExecuted_doFinishFpuMulDiv;
// doFinishMem, after addr translation
method Action setExecuted_doFinishMem(InstTag x, Addr vaddr, Bool access_at_commit, Bool non_mmio_st_done);
method Action setExecuted_doFinishMem(InstTag x,
Addr vaddr,
Data store_data, ByteEn store_data_BE,
Bool access_at_commit, Bool non_mmio_st_done);
`ifdef INCLUDE_TANDEM_VERIF
// Used after a Ld, Lr, Sc, Amo to record reg data
@@ -1009,11 +1036,13 @@ module mkSupReorderBuffer#(
interface setExecuted_doFinishFpuMulDiv = fpuMulDivSetExeIfc;
method Action setExecuted_doFinishMem(
InstTag x, Addr vaddr, Bool access_at_commit, Bool non_mmio_st_done
InstTag x, Addr vaddr, Data store_data, ByteEn store_data_BE, Bool access_at_commit, Bool non_mmio_st_done
) if(
all(id, readVReg(setExeMem_SB_enq)) // ordering: < enq
);
row[x.way][x.ptr].setExecuted_doFinishMem(vaddr, access_at_commit, non_mmio_st_done);
row[x.way][x.ptr].setExecuted_doFinishMem(vaddr,
store_data, store_data_BE,
access_at_commit, non_mmio_st_done);
endmethod
`ifdef INCLUDE_TANDEM_VERIF