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Tweak to workaround internal bsc compiler error

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This commit is contained in:
rsnikhil
2019-04-10 10:36:38 -04:00
parent 5d69e3b178
commit 905583fac9
3 changed files with 1288 additions and 1305 deletions
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2531
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v
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File diff suppressed because it is too large Load Diff

60
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v
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@@ -4746,15 +4746,6 @@ module mkProc(CLK,
.amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27543 &&
!mmioPlatform_reqBE_BIT_0___h27583),
.amoExec(x__h32477));
module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0],
mmioPlatform_reqBE_BIT_4___h27543 &&
mmioPlatform_reqBE_BIT_0___h27583,
2'd0 }),
.amoExec_current_data(64'd0),
.amoExec_in_data(mmioPlatform_reqData__h46242),
.amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27543 &&
!mmioPlatform_reqBE_BIT_0___h27583),
.amoExec(x__h40515));
module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0],
mmioPlatform_reqBE_BIT_4___h27543 &&
mmioPlatform_reqBE_BIT_0___h27583,
@@ -4764,6 +4755,15 @@ module mkProc(CLK,
.amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27543 &&
!mmioPlatform_reqBE_BIT_0___h27583),
.amoExec(x__h38422));
module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0],
mmioPlatform_reqBE_BIT_4___h27543 &&
mmioPlatform_reqBE_BIT_0___h27583,
2'd0 }),
.amoExec_current_data(64'd0),
.amoExec_in_data(mmioPlatform_reqData__h46242),
.amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h27543 &&
!mmioPlatform_reqBE_BIT_0___h27583),
.amoExec(x__h40515));
assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_99_BIT_ETC___d643 =
{ 1'h0,
(mmioPlatform_reqFunc[5:4] == 2'd2) ?
@@ -5627,6 +5627,27 @@ module mkProc(CLK,
3'd7: strb8__h125585 = llc$to_mem_toM_first[575:568];
endcase
end
always@(mmioPlatform_curReq or
result__h46066 or
result__h46094 or result__h46122 or result__h46150)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_45_EQ_0x_ETC___d786 =
result__h46066;
3'h2:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_45_EQ_0x_ETC___d786 =
result__h46094;
3'h4:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_45_EQ_0x_ETC___d786 =
result__h46122;
3'h6:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_45_EQ_0x_ETC___d786 =
result__h46150;
default: IF_mmioPlatform_curReq_94_BITS_2_TO_0_45_EQ_0x_ETC___d786 =
64'd0;
endcase
end
always@(mmioPlatform_curReq or
result__h45825 or
result__h45853 or
@@ -5662,27 +5683,6 @@ module mkProc(CLK,
result__h46021;
endcase
end
always@(mmioPlatform_curReq or
result__h46066 or
result__h46094 or result__h46122 or result__h46150)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_45_EQ_0x_ETC___d786 =
result__h46066;
3'h2:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_45_EQ_0x_ETC___d786 =
result__h46094;
3'h4:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_45_EQ_0x_ETC___d786 =
result__h46122;
3'h6:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_45_EQ_0x_ETC___d786 =
result__h46150;
default: IF_mmioPlatform_curReq_94_BITS_2_TO_0_45_EQ_0x_ETC___d786 =
64'd0;
endcase
end
always@(mmioPlatform_curReq or result__h46191 or result__h46219)
begin
case (mmioPlatform_curReq[2:0])

2
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
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@@ -126,7 +126,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
Bool verbose = False;
// Bluespec: for lightweight verbosity trace
Integer verbosity = 0;
Integer verbosity = 1;
Reg #(Bit #(64)) rg_instret <- mkReg (0);
// func units