Added microarchitectural counter for renamed instructions

This counter is used for the SBC Condition 1 verification

src_Core/CPU/Core.bsv

@@ -238,6 +238,10 @@ instance BitVectorable #(EventsCoreMem, SizeOf#(HpmRpt), EventsCoreMemElements)
    function Vector#(EventsCoreMemElements, HpmRpt) to_vector(EventsCoreMem e) =
       reverse(unpack(pack(e)));
 endinstance
+instance BitVectorable #(EventsTransExe, SizeOf#(SupCnt), EventsTransExeElements) provisos (Bits #(EventsTransExe, m));
+   function Vector#(EventsTransExeElements, SupCnt) to_vector(EventsTransExe e) =
+      reverse(unpack(pack(e)));
+endinstance
 instance BitVectorable #(EventsCache, SizeOf#(HpmRpt), EventsCacheElements) provisos (Bits #(EventsCache, m));
    function Vector#(EventsCacheElements, HpmRpt) to_vector(EventsCache e) =
       reverse(unpack(pack(e)));
@@ -1116,12 +1120,14 @@ module mkCore#(CoreId coreId)(Core);
      Vector #(32, Bit #(Report_Width)) tgc_evts_vec = to_large_vector (events_tgc_reg);
      EventsCache llMem = unpack(pack(events_llc_reg) | pack(l2Tlb.events));
      Vector #(16, Bit #(Report_Width)) llc_evts_vec = to_large_vector (llMem);
+     Vector #(16, Bit #(Report_Width)) trans_exe_evts_vec = to_large_vector (renameStage.events);
 
      let events = append (null_evt, core_evts_vec);
      events = append (events, imem_evts_vec);
      events = append (events, dmem_evts_vec);
      events = append (events, tgc_evts_vec);
      events = append (events, llc_evts_vec);
+     events = append (events, trans_exe_evts_vec);
 
      (* fire_when_enabled, no_implicit_conditions *)
      rule rl_send_perf_evts;

src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv

@@ -45,6 +45,7 @@ import Fifos::*;
 import FIFO::*;
 import Types::*;
 import ProcTypes::*;
+import DReg::*;
 import CCTypes::*;
 import SynthParam::*;
 import Performance::*;
@@ -104,6 +105,11 @@ endinterface
 interface RenameStage;
     // performance count
     method Data getPerf(ExeStagePerfType t);
+
+`ifdef PERFORMANCE_MONITORING
+    method EventsTransExe events;
+`endif
+
     // deadlock check
     interface Get#(RenameStuck) renameInstStuck;
     interface Get#(RenameStuck) renameCorrectPathStuck;
@@ -140,7 +146,9 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
     Count#(Data) specNonMemCycles <- mkCount(0);
 `endif
 `endif
-
+`ifdef PERFORMANCE_MONITORING
+    Reg#(EventsTransExe) events_reg <- mkDReg(unpack(0));
+`endif
     // deadlock check
 `ifdef CHECK_DEADLOCK
     // timer to check deadlock
@@ -579,6 +587,13 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
                                };
         rob.enqPort[0].enq(y);
 
+`ifdef PERFORMANCE_MONITORING
+        EventsTransExe events = unpack(0);
+        $display("Rename-SysInst: 1");
+        events.evt_RENAMED_INST = 1;
+        events_reg <= events;
+`endif
+
         // record if we issue an CSR inst. TODO also for SCRs?
         if(dInst.iType == Csr) begin
             inIfc.issueCsrInstOrInterrupt;
@@ -1161,6 +1176,12 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
             end
         end
 `endif
+`ifdef PERFORMANCE_MONITORING
+        EventsTransExe events = unpack(0);
+        $display("Rename-NormalInst count:", fshow(renameCnt));
+        events.evt_RENAMED_INST = renameCnt;
+        events_reg <= events;
+`endif
 
 `ifdef CHECK_DEADLOCK
         if(doCorrectPath) begin
@@ -1191,6 +1212,10 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
         endcase);
     endmethod
 
+`ifdef PERFORMANCE_MONITORING
+    method events = events_reg;
+`endif
+
 `ifdef INCLUDE_GDB_CONTROL
    method Action debug_halt_req () if (rg_m_halt_req == tagged Invalid);
       rg_m_halt_req <= tagged Valid intrDebugHalt;

src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv

@@ -1049,7 +1049,7 @@ endfunction
 function x addPc(x cap, Bit#(12) inc) provisos (Add#(f, 12, c), CHERICap::CHERICap#(x, a, b, c, d, e)) = setAddrUnsafe(cap, getAddr(cap) + signExtend(inc));
 
 `ifdef PERFORMANCE_MONITORING
-typedef 112 No_Of_Evts;
+typedef 128 No_Of_Evts;
 typedef   8 Report_Width;
 typedef  64 Counter_Width;
 typedef  29 No_Of_Ctrs;
@@ -1120,6 +1120,11 @@ typedef struct {
    HpmRpt evt_MEM_CAP_STORE_TAG_SET;
 } EventsCoreMem deriving (Bits, FShow); // Memory needs more space for reporting delays
 typedef TDiv#(SizeOf#(EventsCoreMem),Report_Width) EventsCoreMemElements;
+
+typedef struct {
+   SupCnt evt_RENAMED_INST;
+} EventsTransExe deriving (Bits, FShow);
+typedef TDiv#(SizeOf#(EventsTransExe),SizeOf#(SupCnt)) EventsTransExeElements;
 `endif
 
 function Bit#(outWidth) hash(Bit#(inWidth) in)