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Update BlueStuff API and Bump BlueStuff and TagController

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This commit is contained in:
Alexandre Joannou
2020-12-01 00:33:48 +00:00
parent 0289bfe17d
commit 98a9c076cd
11 changed files with 254 additions and 175 deletions
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2
libs/BlueStuff

Submodule libs/BlueStuff updated: baf31fb288...b9c76d57ed

2
libs/TagController

Submodule libs/TagController updated: aaa23bc246...f4c5348188

20
src_Core/CPU/LLC_AXI4_Adapter.bsv
View File

@@ -54,9 +54,9 @@ interface LLC_AXI4_Adapter_IFC;
method Action reset;
// Fabric master interface for memory
interface AXI4_Master_Synth #(Wd_MId, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User) mem_master;
interface AXI4_Master #(Wd_MId, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User) mem_master;
endinterface
// ================================================================
@@ -76,7 +76,7 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
// ================================================================
// Fabric request/response
let master_xactor <- mkAXI4_Master_Xactor;
let masterPortShim <- mkAXI4ShimFF;
// For discarding write-responses
CreditCounter_IFC #(4) ctr_wr_rsps_pending <- mkCreditCounter; // Max 15 writes outstanding
@@ -100,7 +100,7 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
arregion: fabric_default_region,
aruser: fabric_default_aruser};
master_xactor.slave.ar.put(mem_req_rd_addr);
masterPortShim.slave.ar.put(mem_req_rd_addr);
// Debugging
if (cfg_verbosity > 1) begin
@@ -134,7 +134,7 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
endrule
rule rl_handle_read_rsps;
let mem_rsp <- get(master_xactor.slave.r);
let mem_rsp <- get(masterPortShim.slave.r);
if (cfg_verbosity > 1) begin
$display ("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", cur_cycle, rg_rd_rsp_beat);
@@ -189,7 +189,7 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
// ================
if (rg_wr_req_beat == 0) begin
// send AXI4 AW flit
master_xactor.slave.aw.put (AXI4_AWFlit {
masterPortShim.slave.aw.put (AXI4_AWFlit {
awid: fabric_default_mid,
awaddr: { wb.addr [63:6], 6'h0 },
awlen: 7, // burst len = awlen+1
@@ -218,7 +218,7 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
Vector #(8, Bit #(8)) line_strb = unpack(pack(wb.byteEn));
Vector #(4, MemTaggedData) line_data = clineToMemTaggedDataVector(wb.data);
// send AXI4 W flit
master_xactor.slave.w.put(AXI4_WFlit {
masterPortShim.slave.w.put(AXI4_WFlit {
wdata: line_data[rg_wr_req_beat[2:1]].data[rg_wr_req_beat[0]],
wstrb: line_strb[rg_wr_req_beat],
wlast: rg_wr_req_beat == 7,
@@ -229,7 +229,7 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
// Discard write-responses from the fabric
rule rl_discard_write_rsp;
let wr_resp <- get(master_xactor.slave.b);
let wr_resp <- get(masterPortShim.slave.b);
if (ctr_wr_rsps_pending.value == 0) begin
$display ("%0d: ERROR: LLC_AXI4_Adapter.rl_discard_write_rsp: unexpected Wr response (ctr_wr_rsps_pending.value == 0)",
@@ -256,7 +256,7 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
endmethod
// Fabric interface for memory
interface mem_master = master_xactor.masterSynth;
interface mem_master = masterPortShim.master;
endmodule
// ================================================================

12
src_Core/CPU/Proc_IFC.bsv
View File

@@ -69,9 +69,9 @@ interface Proc_IFC;
// SoC fabric connections
// Fabric master interface for memory (from LLC)
interface AXI4_Master_Synth #(Wd_MId, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User) master0;
interface AXI4_Master #(Wd_MId, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User) master0;
// Fabric master interface for IO (from MMIOPlatform)
interface AXI4_Master #(Wd_MId_2x3, Wd_Addr, Wd_Data,
@@ -101,9 +101,9 @@ interface Proc_IFC;
// ----------------
// Coherent port into LLC (used by Debug Module, DMA engines, ... to read/write memory)
interface AXI4_Slave_Synth #(Wd_SId_2x3, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User) debug_module_mem_server;
interface AXI4_Slave #(Wd_SId_2x3, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User) debug_module_mem_server;
`ifdef RVFI_DII
interface Toooba_RVFI_DII_Server rvfi_dii_server;

62
src_Core/Core/CoreW.bsv
View File

@@ -164,17 +164,14 @@ module mkCoreW #(Reset dm_power_on_reset)
Proc_IFC proc <- mkProc (reset_by hart0_reset);
// handle uncached interface
let proc_uncached <- toAXI4_Master_Synth(extendIDFields(zeroMasterUserFields(proc.master1), 0));
let proc_uncached = extendIDFields (zeroMasterUserFields (proc.master1), 0);
// Bridge for uncached expernal bus transactions.
let uncached_mem_shim <- mkAXI4ShimFF(reset_by hart0_reset);
let uncached_mem_master <- toAXI4_Master_Synth(extendIDFields(zeroMasterUserFields(uncached_mem_shim.master), 0), reset_by hart0_reset);
// handle cached interface
// AXI4 tagController
TagControllerAXI#(Wd_MId, Wd_Addr, Wd_Data) tagController <- mkTagControllerAXI(reset_by hart0_reset); // TODO double check if reseting like this is good enough
AXI4_Master#(Wd_MId, Wd_Addr, Wd_Data, Wd_AW_User, Wd_W_User, Wd_B_User, Wd_AR_User, Wd_R_User)
tmp2 <- fromAXI4_Master_Synth(proc.master0, reset_by hart0_reset);
mkConnection(tmp2, tagController.slave, reset_by hart0_reset);
mkConnection(proc.master0, tagController.slave, reset_by hart0_reset);
// PLIC (Platform-Level Interrupt Controller)
PLIC_IFC_16_2_7 plic <- mkPLIC_16_2_7;
@@ -355,26 +352,24 @@ module mkCoreW #(Reset dm_power_on_reset)
// Connect the local 2x3 fabric
// Masters on the local 2x3 fabric
Vector#(Num_Masters_2x3,
AXI4_Master_Synth #(Wd_MId_2x3, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User))
master_vector = newVector;
Vector#(Num_Masters_2x3, AXI4_Master #(Wd_MId_2x3, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User))
master_vector = newVector;
//let master_vector = newVector;
master_vector[cpu_uncached_master_num] = proc_uncached;
master_vector[debug_module_sba_master_num] = dm_master_local;
// Slaves on the local 2x3 fabric
// default slave is forwarded out directly to the Core interface
Vector#(Num_Slaves_2x3,
AXI4_Slave_Synth #(Wd_SId_2x3, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User))
slave_vector = newVector;
Vector#(Num_Slaves_2x3, AXI4_Slave #(Wd_SId_2x3, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User))
slave_vector = newVector;
//let slave_vector = newVector;
slave_vector[default_slave_num] <- toAXI4_Slave_Synth(uncached_mem_shim.slave);
slave_vector[default_slave_num] = uncached_mem_shim.slave;
slave_vector[llc_slave_num] = proc.debug_module_mem_server;
slave_vector[plic_slave_num] = plic.axi4_slave;
slave_vector[plic_slave_num] = zeroSlaveUserFields (plic.axi4_slave);
function Vector#(Num_Slaves_2x3, Bool) route_2x3 (Bit#(Wd_Addr) addr);
Vector#(Num_Slaves_2x3, Bool) res = replicate(False);
@@ -389,9 +384,7 @@ module mkCoreW #(Reset dm_power_on_reset)
return res;
endfunction
mkAXI4Bus_Synth (route_2x3, master_vector, slave_vector);
let cached_mem_master <- toAXI4_Master_Synth(tagController.master);
mkAXI4Bus (route_2x3, master_vector, slave_vector);
// ================================================================
// Connect external interrupt lines from PLIC to CPU
@@ -441,10 +434,10 @@ module mkCoreW #(Reset dm_power_on_reset)
// AXI4 Fabric interfaces
// Cached master to Fabric master interface
interface cpu_imem_master = cached_mem_master;
interface cpu_imem_master = tagController.master;
// Uncached master to Fabric master interface
interface cpu_dmem_master = uncached_mem_master;
interface cpu_dmem_master = extendIDFields(zeroMasterUserFields(uncached_mem_shim.master), 0);
// ----------------------------------------------------------------
// External interrupt sources
@@ -493,6 +486,31 @@ module mkCoreW #(Reset dm_power_on_reset)
endmodule: mkCoreW
(* synthesize *)
module mkCoreW_Synth #(Reset dm_power_on_reset)
(CoreW_IFC_Synth #(N_External_Interrupt_Sources));
let core <- mkCoreW (dm_power_on_reset);
let cpu_imem_master_synth <- toAXI4_Master_Synth (core.cpu_imem_master);
let cpu_dmem_master_synth <- toAXI4_Master_Synth (core.cpu_dmem_master);
method set_verbosity = core.set_verbosity;
method start = core.start;
interface cpu_imem_master = cpu_imem_master_synth;
interface cpu_dmem_master = cpu_dmem_master_synth;
interface core_external_interrupt_sources = core.core_external_interrupt_sources;
method nmi_req = core.nmi_req;
`ifdef RVFI_DII
interface rvfi_dii_server = core.Toooba_RVFI_DII_Server rvfi_dii_server;
`endif
`ifdef INCLUDE_GDB_CONTROL
interface dmi = core.dmi;
interface ndm_reset_client = core.ndm_reset_client;
`endif
`ifdef INCLUDE_TANDEM_VERIF
interface tv_verifier_info_get = core.tv_verifier_info_get;
`endif
endmodule
// ================================================================
// 2x3 Fabric for this Core
// Masters: CPU DMem, Debug Module System Bus Access, External access

68
src_Core/Core/CoreW_IFC.bsv
View File

@@ -81,6 +81,74 @@ interface CoreW_IFC #(numeric type t_n_interrupt_sources);
// ----------------------------------------------------------------
// AXI4 Fabric interfaces
// CPU IMem to Fabric master interface
interface AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
0, 0, 0, 0, 0) cpu_imem_master;
// CPU DMem to Fabric master interface
interface AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
0, 0, 0, 0, 0) cpu_dmem_master;
// ----------------------------------------------------------------
// External interrupt sources
interface Vector #(t_n_interrupt_sources, PLIC_Source_IFC) core_external_interrupt_sources;
// ----------------------------------------------------------------
// Non-maskable interrupt request
(* always_ready, always_enabled *)
method Action nmi_req (Bool set_not_clear);
`ifdef RVFI_DII
interface Toooba_RVFI_DII_Server rvfi_dii_server;
`endif
`ifdef INCLUDE_GDB_CONTROL
// ----------------------------------------------------------------
// Optional Debug Module interfaces
// ----------------
// DMI (Debug Module Interface) facing remote debugger
interface DMI dmi;
// ----------------
// Facing Platform
// Non-Debug-Module Reset (reset all except DM)
interface Client #(Bool, Bool) ndm_reset_client;
`endif
`ifdef INCLUDE_TANDEM_VERIF
// ----------------------------------------------------------------
// Optional Tandem Verifier interface output tuples (n,vb),
// where 'vb' is a vector of bytes
// with relevant bytes in locations [0]..[n-1]
interface Get #(Info_CPU_to_Verifier) tv_verifier_info_get;
`endif
endinterface
// ================================================================
// The Synthesizable CoreW interface (same with Synth AXI)
interface CoreW_IFC_Synth #(numeric type t_n_interrupt_sources);
// ----------------------------------------------------------------
// Debugging: set core's verbosity
method Action set_verbosity (Bit #(4) verbosity, Bit #(64) logdelay);
// ----------------------------------------------------------------
// Start
method Action start (Bool is_running, Bit #(64) tohost_addr, Bit #(64) fromhost_addr);
// ----------------------------------------------------------------
// AXI4 Fabric interfaces
// CPU IMem to Fabric master interface
interface AXI4_Master_Synth #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
0, 0, 0, 0, 0) cpu_imem_master;

35
src_Core/PLIC/PLIC.bsv
View File

@@ -98,9 +98,8 @@ interface PLIC_IFC #(numeric type t_n_external_sources,
method Action set_addr_map (Bit #(64) addr_base, Bit #(64) addr_lim);
// Memory-mapped access
interface AXI4_Slave_Synth #(Wd_SId_2x3, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User) axi4_slave;
interface AXI4_Slave #( Wd_SId_2x3, Wd_Addr, Wd_Data, 0, 0, 0, 0, 0)
axi4_slave;
// sources
interface Vector #(t_n_external_sources, PLIC_Source_IFC) v_sources;
@@ -142,9 +141,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority))
Reg #(Bit #(64)) rg_addr_lim <- mkRegU;
// Connector to AXI4 fabric
AXI4_Slave_Width_Xactor#(Wd_SId_2x3, Wd_Addr, Wd_Data_Periph, Wd_Data,
Wd_AW_User_Periph, Wd_W_User_Periph, Wd_B_User_Periph, Wd_AR_User_Periph, Wd_R_User_Periph,
Wd_AW_User, Wd_W_User, Wd_B_User, Wd_AR_User, Wd_R_User) slave_xactor <- mkAXI4_Slave_Zeroing_Xactor;
let slavePortShim <- mkAXI4ShimFF;
// ----------------
// Per-interrupt source state
@@ -246,7 +243,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority))
for (Integer source_id = 0; source_id < n_sources; source_id = source_id + 1)
vvrg_ie [target_id][source_id] <= False;
slave_xactor.clear;
slavePortShim.clear;
f_reset_rsps.enq (?);
endrule
@@ -261,7 +258,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority))
rule rl_process_rd_req (! f_reset_reqs.notEmpty);
let rda <- get(slave_xactor.master.ar);
let rda <- get(slavePortShim.master.ar);
if (cfg_verbosity > 1) begin
$display ("%0d: PLIC.rl_process_rd_req:", cur_cycle);
$display (" ", fshow (rda));
@@ -404,11 +401,11 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority))
// Send read-response to bus
Fabric_Data x = truncate (rdata);
let rdr = AXI4_RFlit {rid: rda.arid,
rdata: x,
rresp: rresp,
rlast: True,
ruser: rda.aruser}; // XXX This requires that Wd_AR_User == Wd_R_User
slave_xactor.master.r.put(rdr);
rdata: x,
rresp: rresp,
rlast: True,
ruser: rda.aruser}; // XXX This requires that Wd_AR_User == Wd_R_User
slavePortShim.master.r.put(rdr);
if (cfg_verbosity > 1) begin
$display ("%0d: PLIC.rl_process_rd_req", cur_cycle);
@@ -424,8 +421,8 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority))
rule rl_process_wr_req (! f_reset_reqs.notEmpty);
let wra <- get(slave_xactor.master.aw);
let wrd <- get(slave_xactor.master.w);
let wra <- get(slavePortShim.master.aw);
let wrd <- get(slavePortShim.master.w);
if (cfg_verbosity > 1) begin
$display ("%0d: PLIC.rl_process_wr_req", cur_cycle);
$display (" ", fshow (wra));
@@ -551,9 +548,9 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority))
// Send write-response to bus
let wrr = AXI4_BFlit {bid: wra.awid,
bresp: bresp,
buser: wra.awuser}; // XXX This requires that Wd_AW_User == Wd_B_User
slave_xactor.master.b.put(wrr);
bresp: bresp,
buser: wra.awuser}; // XXX This requires that Wd_AW_User == Wd_B_User
slavePortShim.master.b.put(wrr);
if (cfg_verbosity > 1) begin
$display ("%0d: PLIC.AXI4.rl_process_wr_req", cur_cycle);
@@ -628,7 +625,7 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority))
endmethod
// Memory-mapped access
interface axi4_slave = slave_xactor.slaveSynth;
interface axi4_slave = slavePortShim.slave;
// sources
interface v_sources = genWith (fn_mk_PLIC_Source_IFC);

42
src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv
View File

@@ -131,9 +131,9 @@ module mkLLCDmaConnect #(
DmaServer#(LLCDmaReqId) llc,
// MemLoaderMemClient memLoader, // REPLACED BY AXI4_Slave_interface
Vector#(CoreNum, TlbMemClient) tlb
)(AXI4_Slave_Synth #(Wd_SId_2x3, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User)) provisos (
)(AXI4_Slave #(Wd_SId_2x3, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User)) provisos (
Alias#(dmaRqT, DmaRq#(LLCDmaReqId))
);
Bool verbose = False;
@@ -143,8 +143,8 @@ module mkLLCDmaConnect #(
// When debugger reads a word, request a line from LLC, and remember dword-in-line here
FIFOF #(Bit #(3)) f_dword_in_line <- mkFIFOF;
// Slave transactor for requests from Debug Module
let axi4_slave_xactor <- mkAXI4_Slave_Xactor;
// Connector to AXI4 fabric
let slavePortShim <- mkAXI4ShimFF;
// ================================================================
// These regs are a 1-location local cache for an LLC Cache Line,
@@ -163,10 +163,10 @@ module mkLLCDmaConnect #(
// Respond to store-requests from the external client on store-hit
rule rl_handle_MemLoader_st_req ( ( (rg_cacheline_cache_state == CACHELINE_CACHE_CLEAN)
|| (rg_cacheline_cache_state == CACHELINE_CACHE_DIRTY))
&& (fn_addr_is_in_line (axi4_slave_xactor.master.aw.peek.awaddr,
&& (fn_addr_is_in_line (slavePortShim.master.aw.peek.awaddr,
rg_cacheline_cache_addr)));
let wr_addr <- get (axi4_slave_xactor.master.aw);
let wr_data <- get (axi4_slave_xactor.master.w);
let wr_addr <- get (slavePortShim.master.aw);
let wr_data <- get (slavePortShim.master.w);
// Modify relevant bytes of relevant dword
let newLine = setDataAtBE( rg_cacheline_cache_data
@@ -178,7 +178,7 @@ module mkLLCDmaConnect #(
rg_cacheline_cache_dirty_delay <= '1; // start write-back delay countdown
// Send response to external client
axi4_slave_xactor.master.b.put(AXI4_BFlit{
slavePortShim.master.b.put(AXI4_BFlit{
bid: wr_addr.awid, // TODO: change uniformly to Fabric_id
bresp: OKAY,
buser: ?
@@ -198,14 +198,14 @@ module mkLLCDmaConnect #(
// Responds to load-requests from the external client on load-hit
rule rl_handle_MemLoader_ld_req ( ( (rg_cacheline_cache_state == CACHELINE_CACHE_CLEAN)
|| (rg_cacheline_cache_state == CACHELINE_CACHE_DIRTY))
&& (fn_addr_is_in_line (axi4_slave_xactor.master.ar.peek.araddr,
&& (fn_addr_is_in_line (slavePortShim.master.ar.peek.araddr,
rg_cacheline_cache_addr)));
let rd_addr <- get (axi4_slave_xactor.master.ar);
let rd_addr <- get (slavePortShim.master.ar);
let dword = getDataAt( rg_cacheline_cache_data
, getCLineDataSel(rd_addr.araddr));
// Send response to external client
axi4_slave_xactor.master.r.put(AXI4_RFlit{
slavePortShim.master.r.put(AXI4_RFlit{
rid: rd_addr.arid,
rdata: dword,
rresp: OKAY,
@@ -255,12 +255,12 @@ module mkLLCDmaConnect #(
// Initiate writeback if dirty and next request is store-miss
rule rl_cacheline_cache_writeback_st_miss ( (rg_cacheline_cache_state == CACHELINE_CACHE_DIRTY)
&& (! fn_addr_is_in_line (axi4_slave_xactor.master.aw.peek.awaddr,
&& (! fn_addr_is_in_line (slavePortShim.master.aw.peek.awaddr,
rg_cacheline_cache_addr)));
if (verbosity >= 2) begin
$display ("%0d: %m.rl_cacheline_cache_writeback_st_miss.", cur_cycle);
$display (" Old line addr %0h", rg_cacheline_cache_addr);
$display (" New addr %0h", axi4_slave_xactor.master.aw.peek.awaddr);
$display (" New addr %0h", slavePortShim.master.aw.peek.awaddr);
end
fa_writeback;
@@ -269,12 +269,12 @@ module mkLLCDmaConnect #(
// Initiate writeback if dirty and next request is load-miss
rule rl_cacheline_cache_writeback_ld_miss ( (rg_cacheline_cache_state == CACHELINE_CACHE_DIRTY)
&& (! fn_addr_is_in_line (axi4_slave_xactor.master.ar.peek.araddr,
&& (! fn_addr_is_in_line (slavePortShim.master.ar.peek.araddr,
rg_cacheline_cache_addr)));
if (verbosity >= 2) begin
$display ("%0d: %m.rl_cacheline_cache_writeback_ld_miss.", cur_cycle);
$display (" Old line addr %0h", rg_cacheline_cache_addr);
$display (" New addr %0h", axi4_slave_xactor.master.aw.peek.awaddr);
$display (" New addr %0h", slavePortShim.master.aw.peek.awaddr);
end
fa_writeback;
@@ -313,9 +313,9 @@ module mkLLCDmaConnect #(
// Initiate reload when cacheline_cache is clean on store-miss
rule rl_cacheline_cache_reload_req_st ( (rg_cacheline_cache_state == CACHELINE_CACHE_CLEAN)
&& (! fn_addr_is_in_line (axi4_slave_xactor.master.aw.peek.awaddr,
&& (! fn_addr_is_in_line (slavePortShim.master.aw.peek.awaddr,
rg_cacheline_cache_addr)));
let addr = axi4_slave_xactor.master.aw.peek.awaddr;
let addr = slavePortShim.master.aw.peek.awaddr;
if (verbosity >= 2) begin
$display ("%0d: %m.rl_cacheline_cache_reload_req_st for addr %0h", cur_cycle, addr);
@@ -327,9 +327,9 @@ module mkLLCDmaConnect #(
// Initiate reload when cacheline_cache is clean on load-miss
rule rl_cacheline_cache_reload_req_ld ( (rg_cacheline_cache_state == CACHELINE_CACHE_CLEAN)
&& (! fn_addr_is_in_line (axi4_slave_xactor.master.ar.peek.araddr,
&& (! fn_addr_is_in_line (slavePortShim.master.ar.peek.araddr,
rg_cacheline_cache_addr)));
let addr = axi4_slave_xactor.master.ar.peek.araddr;
let addr = slavePortShim.master.ar.peek.araddr;
if (verbosity >= 2) begin
$display ("%0d: %m.rl_cacheline_cache_reload_req_ld for addr %0h", cur_cycle, addr);
@@ -424,5 +424,5 @@ module mkLLCDmaConnect #(
// ================================================================
// INTERFACE
return axi4_slave_xactor.slaveSynth;
return slavePortShim.slave;
endmodule

110
src_Testbench/SoC/Boot_ROM.bsv
View File

@@ -64,11 +64,30 @@ interface Boot_ROM_IFC;
method Action set_addr_map (Fabric_Addr addr_base, Fabric_Addr addr_lim);
// Main Fabric Reqs/Rsps
interface AXI4_Slave_Synth #(Wd_SId, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User) slave;
interface AXI4_Slave #(Wd_SId, Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0)
slave;
endinterface
// ================================================================
// Some local help-functions
function Bool fn_addr_is_aligned (Fabric_Addr addr, AXI4_Size arsize);
if (arsize == 1) return True;
else if (arsize == 2) return (addr [0] == 1'b_0);
else if (arsize == 4) return (addr [1:0] == 2'b_00);
else if (arsize == 8) return (addr [2:0] == 3'b_000);
else return False;
endfunction
function Bool fn_addr_is_in_range (Fabric_Addr base, Fabric_Addr addr, Fabric_Addr lim);
return ((base <= addr) && (addr < lim));
endfunction
function Bool fn_addr_is_ok (Fabric_Addr base, Fabric_Addr addr, Fabric_Addr lim, AXI4_Size arsize);
return ( fn_addr_is_aligned (addr, arsize)
&& fn_addr_is_in_range (base, addr, lim));
endfunction
// ================================================================
(* synthesize *)
@@ -85,30 +104,10 @@ module mkBoot_ROM (Boot_ROM_IFC);
// ----------------
// Connector to fabric
AXI4_Slave_Width_Xactor#(Wd_SId, Wd_Addr, Wd_Data_Periph, Wd_Data,
Wd_AW_User_Periph, Wd_W_User_Periph, Wd_B_User_Periph, Wd_AR_User_Periph, Wd_R_User_Periph,
Wd_AW_User, Wd_W_User, Wd_B_User, Wd_AR_User, Wd_R_User) slave_xactor <- mkAXI4_Slave_Zeroing_Xactor;
let slavePortShim <- mkAXI4ShimFF;
// ----------------
function Bool fn_addr_is_aligned (Fabric_Addr addr);
if (valueOf (Wd_Data) == 32)
return (addr [1:0] == 2'b_00);
else if (valueOf (Wd_Data) == 64)
return (addr [2:0] == 3'b_000);
else
return False;
endfunction
function Bool fn_addr_is_in_range (Fabric_Addr base, Fabric_Addr addr, Fabric_Addr lim);
return ((base <= addr) && (addr < lim));
endfunction
function Bool fn_addr_is_ok (Fabric_Addr base, Fabric_Addr addr, Fabric_Addr lim);
return ( fn_addr_is_aligned (addr)
&& fn_addr_is_in_range (base, addr, lim));
endfunction
// ================================================================
// BEHAVIOR
@@ -116,34 +115,37 @@ module mkBoot_ROM (Boot_ROM_IFC);
// Handle fabric read requests
rule rl_process_rd_req (rg_module_ready);
let rda <- get(slave_xactor.master.ar);
let byte_addr = rda.araddr - rg_addr_base;
let rda <- get(slavePortShim.master.ar);
AXI4_Resp rresp = OKAY;
Bit #(64) data64 = 0;
if (! fn_addr_is_ok (rg_addr_base, rda.araddr, rg_addr_lim)) begin
if (! fn_addr_is_ok (rg_addr_base, rda.araddr, rg_addr_lim, rda.arsize)) begin
rresp = SLVERR;
$display ("%0d: ERROR: Boot_ROM.rl_process_rd_req: unrecognized addr", cur_cycle);
$display ("%0d: ERROR: Boot_ROM.rl_process_rd_req: unrecognized or misaligned addr",
cur_cycle);
$display (" ", fshow (rda));
end
else if (rda.araddr [2:0] == 3'b0) begin
Bit #(32) d0 = fn_read_ROM_0 (byte_addr);
Bit #(32) d1 = fn_read_ROM_4 (byte_addr + 4);
data64 = { d1, d0 };
end
else begin // ((valueOf (Wd_Data) == 32) && (rda.addr [1:0] == 2'b_00))
Bit #(32) d1 = fn_read_ROM_4 (byte_addr);
data64 = { 0, d1 };
else begin
// Byte offset
let byte_offset = rda.araddr - rg_addr_base;
let rom_addr_0 = (byte_offset & (~ 'b_111));
Bit #(32) d0 = fn_read_ROM_0 (rom_addr_0);
let rom_addr_4 = (rom_addr_0 | 'b_100);
Bit #(32) d4 = fn_read_ROM_4 (rom_addr_4);
if ((valueOf (Wd_Data) == 32) && (byte_offset [2] == 1'b_1))
data64 = { 0, d4 };
else
data64 = { d4, d0 };
end
Bit #(Wd_Data) rdata = truncate (data64);
let rdr = AXI4_RFlit {rid: rda.arid,
rdata: rdata,
rresp: rresp,
rlast: True,
ruser: rda.aruser}; // XXX This requires that Wd_AR_User == Wd_R_User
slave_xactor.master.r.put(rdr);
Bit #(Wd_Data_Periph) rdata = truncate (data64);
AXI4_RFlit#(Wd_SId, Wd_Data_Periph, 0) rdr = AXI4_RFlit {rid: rda.arid,
rdata: rdata,
rresp: rresp,
rlast: True,
ruser: 0};
slavePortShim.master.r.put(rdr);
if (verbosity > 0) begin
$display ("%0d: Boot_ROM.rl_process_rd_req: ", cur_cycle);
@@ -156,20 +158,21 @@ module mkBoot_ROM (Boot_ROM_IFC);
// Handle fabric write requests: ignore all of them (this is a ROM)
rule rl_process_wr_req (rg_module_ready);
let wra <- get(slave_xactor.master.aw);
let wrd <- get(slave_xactor.master.w);
let wra <- get(slavePortShim.master.aw);
let wrd <- get(slavePortShim.master.w);
AXI4_Resp bresp = OKAY;
if (! fn_addr_is_ok (rg_addr_base, wra.awaddr, rg_addr_lim)) begin
if (! fn_addr_is_ok (rg_addr_base, wra.awaddr, rg_addr_lim, wra.awsize)) begin
bresp = SLVERR;
$display ("%0d: ERROR: Boot_ROM.rl_process_wr_req: unrecognized addr", cur_cycle);
$display ("%0d: ERROR: Boot_ROM.rl_process_wr_req: unrecognized or misaligned addr",
cur_cycle);
$display (" ", fshow (wra));
end
let wrr = AXI4_BFlit {bid: wra.awid,
bresp: bresp,
buser: wra.awuser}; // XXX This requires that Wd_AW_User == Wd_B_User
slave_xactor.master.b.put(wrr);
AXI4_BFlit#(Wd_SId, 0) wrr = AXI4_BFlit {bid: wra.awid,
bresp: bresp,
buser: 0};
slavePortShim.master.b.put(wrr);
if (verbosity > 0) begin
$display ("%0d: Boot_ROM.rl_process_wr_req; ignoring all writes", cur_cycle);
@@ -206,14 +209,13 @@ module mkBoot_ROM (Boot_ROM_IFC);
rg_addr_base <= addr_base;
rg_addr_lim <= addr_lim;
rg_module_ready <= True;
slave_xactor.clear;
if (verbosity > 0) begin
$display ("%0d: Boot_ROM.set_addr_map: base 0x%0h lim 0x%0h", cur_cycle, addr_base, addr_lim);
end
endmethod
// Main Fabric Reqs/Rsps
interface slave = slave_xactor.slaveSynth;
interface slave = slavePortShim.slave;
endmodule
// ================================================================

34
src_Testbench/SoC/Mem_Controller.bsv
View File

@@ -207,8 +207,8 @@ interface Mem_Controller_IFC;
method Action set_addr_map (Fabric_Addr addr_base, Fabric_Addr addr_lim);
// Main Fabric Reqs/Rsps
interface AXI4_Slave_Synth #(Wd_SId, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User, Wd_AR_User, Wd_R_User) slave;
interface AXI4_Slave #(Wd_SId, Wd_Addr, Wd_Data, 0, 0, 0, 0, 0)
slave;
// To raw memory (outside the SoC)
interface MemoryClient #(Bits_per_Raw_Mem_Addr, Bits_per_Raw_Mem_Word) to_raw_mem;
@@ -269,9 +269,7 @@ module mkMem_Controller (Mem_Controller_IFC);
FIFOF #(Bit #(0)) f_reset_rsps <- mkFIFOF;
// Communication with fabric
AXI4_Slave_Width_Xactor#(Wd_SId, Wd_Addr, Wd_Data_Periph, Wd_Data,
Wd_AW_User_Periph, Wd_W_User_Periph, Wd_B_User_Periph, Wd_AR_User_Periph, Wd_R_User_Periph,
Wd_AW_User, Wd_W_User, Wd_B_User, Wd_AR_User, Wd_R_User) slave_xactor <- mkAXI4_Slave_Zeroing_Xactor;
let slavePortShim <- mkAXI4ShimFF;
// Requests merged from the (WrA, WrD) and RdA channels
FIFOF #(Req) f_reqs <- mkPipelineFIFOF;
@@ -304,7 +302,7 @@ module mkMem_Controller (Mem_Controller_IFC);
function Action fa_reset_actions;
action
slave_xactor.clear;
slavePortShim.clear;
f_raw_mem_reqs.clear;
f_raw_mem_rsps.clear;
rg_status <= 0;
@@ -345,7 +343,7 @@ module mkMem_Controller (Mem_Controller_IFC);
// Merge requests into a single queue, prioritizing reads over writes
rule rl_merge_rd_req;
let rda <- get(slave_xactor.master.ar);
let rda <- get(slavePortShim.master.ar);
let req = Req {req_op: REQ_OP_RD,
id: rda.arid,
addr: rda.araddr,
@@ -370,8 +368,8 @@ module mkMem_Controller (Mem_Controller_IFC);
(* descending_urgency = "rl_merge_rd_req, rl_merge_wr_req" *)
rule rl_merge_wr_req;
let wra <- get(slave_xactor.master.aw);
let wrd <- get(slave_xactor.master.w);
let wra <- get(slavePortShim.master.aw);
let wrd <- get(slavePortShim.master.w);
let req = Req {req_op: REQ_OP_WR,
id: wra.awid,
addr: wra.awaddr,
@@ -504,8 +502,8 @@ module mkMem_Controller (Mem_Controller_IFC);
rdata: rdata,
rresp: OKAY,
rlast: True,
ruser: f_reqs.first.user}; // XXX This requires that Wd_AR_User == Wd_R_User
slave_xactor.master.r.put(rdr);
ruser: 0'b0};
slavePortShim.master.r.put(rdr);
f_reqs.deq;
if (cfg_verbosity > 1) begin
@@ -546,8 +544,8 @@ module mkMem_Controller (Mem_Controller_IFC);
let wrr = AXI4_BFlit {bid: f_reqs.first.id,
bresp: OKAY,
buser: f_reqs.first.user}; // XXX This requires that Wd_AW_User == Wd_B_User
slave_xactor.master.b.put(wrr);
buser: 0'b0};
slavePortShim.master.b.put(wrr);
f_reqs.deq;
if (cfg_verbosity > 1) begin
@@ -616,8 +614,8 @@ module mkMem_Controller (Mem_Controller_IFC);
rdata: rdata, // for debugging only
rresp: SLVERR,
rlast: True,
ruser: f_reqs.first.user}; // XXX This requires that Wd_AR_User == Wd_R_User
slave_xactor.master.r.put(rdr);
ruser: 0'b0};
slavePortShim.master.r.put(rdr);
f_reqs.deq;
$write ("%0d: ERROR: Mem_Controller:", cur_cycle);
@@ -635,8 +633,8 @@ module mkMem_Controller (Mem_Controller_IFC);
&& (f_reqs.first.req_op == REQ_OP_WR));
let wrr = AXI4_BFlit {bid: f_reqs.first.id,
bresp: SLVERR,
buser: f_reqs.first.user}; // XXX This requires that Wd_AW_User == Wd_B_User
slave_xactor.master.b.put(wrr);
buser: 0'b0};
slavePortShim.master.b.put(wrr);
f_reqs.deq;
$write ("%0d: ERROR: Mem_Controller:", cur_cycle);
@@ -671,7 +669,7 @@ module mkMem_Controller (Mem_Controller_IFC);
endmethod
// Main Fabric Reqs/Rsps
interface slave = slave_xactor.slaveSynth;
interface slave = slavePortShim.slave;
// To raw memory (outside the SoC)
interface to_raw_mem = toGPClient (f_raw_mem_reqs, f_raw_mem_rsps);

42
src_Testbench/SoC/SoC_Top.bsv
View File

@@ -153,16 +153,14 @@ module mkSoC_Top #(Reset dm_power_on_reset)
// SoC Boot ROM
Boot_ROM_IFC boot_rom <- mkBoot_ROM;
// AXI4 Deburster in front of Boot_ROM
AXI4_Shim#(Wd_SId, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User, Wd_AR_User, Wd_R_User)
boot_rom_axi4_deburster <- mkBurstToNoBurst;
AXI4_Shim#(Wd_SId, Wd_Addr, Wd_Data, 0, 0, 0, 0, 0)
boot_rom_axi4_deburster <- mkBurstToNoBurst;
// SoC Memory
Mem_Controller_IFC mem0_controller <- mkMem_Controller;
// AXI4 Deburster in front of SoC Memory
AXI4_Shim#(Wd_SId, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User, Wd_AR_User, Wd_R_User)
mem0_controller_axi4_deburster <- mkBurstToNoBurst;
AXI4_Shim#(Wd_SId, Wd_Addr, Wd_Data, 0, 0, 0, 0, 0)
mem0_controller_axi4_deburster <- mkBurstToNoBurst;
// SoC IPs
UART_IFC uart0 <- mkUART;
@@ -176,9 +174,9 @@ module mkSoC_Top #(Reset dm_power_on_reset)
// SoC fabric master connections
// Note: see 'SoC_Map' for 'master_num' definitions
Vector#(Num_Masters, AXI4_Master_Synth #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
0, 0, 0, 0, 0))
master_vector = newVector;
Vector#(Num_Masters, AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
0, 0, 0, 0, 0))
master_vector = newVector;
// CPU IMem master to fabric
master_vector[imem_master_num] = corew.cpu_imem_master;
@@ -190,30 +188,28 @@ module mkSoC_Top #(Reset dm_power_on_reset)
// SoC fabric slave connections
// Note: see 'SoC_Map' for 'slave_num' definitions
Vector#(Num_Slaves, AXI4_Slave_Synth #(Wd_SId, Wd_Addr, Wd_Data,
0, 0, 0, 0, 0))
slave_vector = newVector;
Vector#(Num_Slaves, Range#(Wd_Addr)) route_vector = newVector;
Vector#(Num_Slaves, AXI4_Slave #(Wd_SId, Wd_Addr, Wd_Data,
0, 0, 0, 0, 0))
slave_vector = newVector;
Vector#(Num_Slaves, Range#(Wd_Addr)) route_vector = newVector;
// Fabric to Boot ROM
let br <- fromAXI4_Slave_Synth(boot_rom.slave);
mkConnection(boot_rom_axi4_deburster.master, br);
slave_vector[boot_rom_slave_num] <- toAXI4_Slave_Synth(zeroSlaveUserFields(boot_rom_axi4_deburster.slave));
mkConnection(boot_rom_axi4_deburster.master, boot_rom.slave);
slave_vector[boot_rom_slave_num] = boot_rom_axi4_deburster.slave;
route_vector[boot_rom_slave_num] = soc_map.m_boot_rom_addr_range;
// Fabric to Mem Controller
let mem <- fromAXI4_Slave_Synth(mem0_controller.slave);
mkConnection(mem0_controller_axi4_deburster.master, mem);
slave_vector[mem0_controller_slave_num] <- toAXI4_Slave_Synth(zeroSlaveUserFields(mem0_controller_axi4_deburster.slave));
mkConnection(mem0_controller_axi4_deburster.master, mem0_controller.slave);
slave_vector[mem0_controller_slave_num] = mem0_controller_axi4_deburster.slave;
route_vector[mem0_controller_slave_num] = soc_map.m_mem0_controller_addr_range;
// Fabric to UART0
slave_vector[uart0_slave_num] <- toAXI4_Slave_Synth(zeroSlaveUserFields(uart0.slave));
slave_vector[uart0_slave_num] = zeroSlaveUserFields(uart0.slave);
route_vector[uart0_slave_num] = soc_map.m_uart0_addr_range;
`ifdef INCLUDE_ACCEL0
// Fabric to accel0
slave_vector[accel0_slave_num] <- liftAXI4_Slave_Synth(zeroSlaveUserFields, accel0.slave);
slave_vector[accel0_slave_num] = zeroSlaveUserFields (accel0.slave);
route_vector[accel0_slave_num] = soc_map.m_accel0_addr_range;
`endif
@@ -225,8 +221,8 @@ module mkSoC_Top #(Reset dm_power_on_reset)
`endif
// SoC Fabric
let bus <- mkAXI4Bus_Synth (routeFromMappingTable(route_vector),
master_vector, slave_vector);
let bus <- mkAXI4Bus (routeFromMappingTable(route_vector),
master_vector, slave_vector);
// ----------------
// Connect interrupt sources for CPU external interrupt request inputs.