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Update BlueStuff API and Bump BlueStuff and TagController

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This commit is contained in:
Alexandre Joannou
2020-12-01 00:33:48 +00:00
parent 0289bfe17d
commit 98a9c076cd
11 changed files with 254 additions and 175 deletions
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110
src_Testbench/SoC/Boot_ROM.bsv
View File

@@ -64,11 +64,30 @@ interface Boot_ROM_IFC;
method Action set_addr_map (Fabric_Addr addr_base, Fabric_Addr addr_lim);
// Main Fabric Reqs/Rsps
interface AXI4_Slave_Synth #(Wd_SId, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User) slave;
interface AXI4_Slave #(Wd_SId, Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0)
slave;
endinterface
// ================================================================
// Some local help-functions
function Bool fn_addr_is_aligned (Fabric_Addr addr, AXI4_Size arsize);
if (arsize == 1) return True;
else if (arsize == 2) return (addr [0] == 1'b_0);
else if (arsize == 4) return (addr [1:0] == 2'b_00);
else if (arsize == 8) return (addr [2:0] == 3'b_000);
else return False;
endfunction
function Bool fn_addr_is_in_range (Fabric_Addr base, Fabric_Addr addr, Fabric_Addr lim);
return ((base <= addr) && (addr < lim));
endfunction
function Bool fn_addr_is_ok (Fabric_Addr base, Fabric_Addr addr, Fabric_Addr lim, AXI4_Size arsize);
return ( fn_addr_is_aligned (addr, arsize)
&& fn_addr_is_in_range (base, addr, lim));
endfunction
// ================================================================
(* synthesize *)
@@ -85,30 +104,10 @@ module mkBoot_ROM (Boot_ROM_IFC);
// ----------------
// Connector to fabric
AXI4_Slave_Width_Xactor#(Wd_SId, Wd_Addr, Wd_Data_Periph, Wd_Data,
Wd_AW_User_Periph, Wd_W_User_Periph, Wd_B_User_Periph, Wd_AR_User_Periph, Wd_R_User_Periph,
Wd_AW_User, Wd_W_User, Wd_B_User, Wd_AR_User, Wd_R_User) slave_xactor <- mkAXI4_Slave_Zeroing_Xactor;
let slavePortShim <- mkAXI4ShimFF;
// ----------------
function Bool fn_addr_is_aligned (Fabric_Addr addr);
if (valueOf (Wd_Data) == 32)
return (addr [1:0] == 2'b_00);
else if (valueOf (Wd_Data) == 64)
return (addr [2:0] == 3'b_000);
else
return False;
endfunction
function Bool fn_addr_is_in_range (Fabric_Addr base, Fabric_Addr addr, Fabric_Addr lim);
return ((base <= addr) && (addr < lim));
endfunction
function Bool fn_addr_is_ok (Fabric_Addr base, Fabric_Addr addr, Fabric_Addr lim);
return ( fn_addr_is_aligned (addr)
&& fn_addr_is_in_range (base, addr, lim));
endfunction
// ================================================================
// BEHAVIOR
@@ -116,34 +115,37 @@ module mkBoot_ROM (Boot_ROM_IFC);
// Handle fabric read requests
rule rl_process_rd_req (rg_module_ready);
let rda <- get(slave_xactor.master.ar);
let byte_addr = rda.araddr - rg_addr_base;
let rda <- get(slavePortShim.master.ar);
AXI4_Resp rresp = OKAY;
Bit #(64) data64 = 0;
if (! fn_addr_is_ok (rg_addr_base, rda.araddr, rg_addr_lim)) begin
if (! fn_addr_is_ok (rg_addr_base, rda.araddr, rg_addr_lim, rda.arsize)) begin
rresp = SLVERR;
$display ("%0d: ERROR: Boot_ROM.rl_process_rd_req: unrecognized addr", cur_cycle);
$display ("%0d: ERROR: Boot_ROM.rl_process_rd_req: unrecognized or misaligned addr",
cur_cycle);
$display (" ", fshow (rda));
end
else if (rda.araddr [2:0] == 3'b0) begin
Bit #(32) d0 = fn_read_ROM_0 (byte_addr);
Bit #(32) d1 = fn_read_ROM_4 (byte_addr + 4);
data64 = { d1, d0 };
end
else begin // ((valueOf (Wd_Data) == 32) && (rda.addr [1:0] == 2'b_00))
Bit #(32) d1 = fn_read_ROM_4 (byte_addr);
data64 = { 0, d1 };
else begin
// Byte offset
let byte_offset = rda.araddr - rg_addr_base;
let rom_addr_0 = (byte_offset & (~ 'b_111));
Bit #(32) d0 = fn_read_ROM_0 (rom_addr_0);
let rom_addr_4 = (rom_addr_0 | 'b_100);
Bit #(32) d4 = fn_read_ROM_4 (rom_addr_4);
if ((valueOf (Wd_Data) == 32) && (byte_offset [2] == 1'b_1))
data64 = { 0, d4 };
else
data64 = { d4, d0 };
end
Bit #(Wd_Data) rdata = truncate (data64);
let rdr = AXI4_RFlit {rid: rda.arid,
rdata: rdata,
rresp: rresp,
rlast: True,
ruser: rda.aruser}; // XXX This requires that Wd_AR_User == Wd_R_User
slave_xactor.master.r.put(rdr);
Bit #(Wd_Data_Periph) rdata = truncate (data64);
AXI4_RFlit#(Wd_SId, Wd_Data_Periph, 0) rdr = AXI4_RFlit {rid: rda.arid,
rdata: rdata,
rresp: rresp,
rlast: True,
ruser: 0};
slavePortShim.master.r.put(rdr);
if (verbosity > 0) begin
$display ("%0d: Boot_ROM.rl_process_rd_req: ", cur_cycle);
@@ -156,20 +158,21 @@ module mkBoot_ROM (Boot_ROM_IFC);
// Handle fabric write requests: ignore all of them (this is a ROM)
rule rl_process_wr_req (rg_module_ready);
let wra <- get(slave_xactor.master.aw);
let wrd <- get(slave_xactor.master.w);
let wra <- get(slavePortShim.master.aw);
let wrd <- get(slavePortShim.master.w);
AXI4_Resp bresp = OKAY;
if (! fn_addr_is_ok (rg_addr_base, wra.awaddr, rg_addr_lim)) begin
if (! fn_addr_is_ok (rg_addr_base, wra.awaddr, rg_addr_lim, wra.awsize)) begin
bresp = SLVERR;
$display ("%0d: ERROR: Boot_ROM.rl_process_wr_req: unrecognized addr", cur_cycle);
$display ("%0d: ERROR: Boot_ROM.rl_process_wr_req: unrecognized or misaligned addr",
cur_cycle);
$display (" ", fshow (wra));
end
let wrr = AXI4_BFlit {bid: wra.awid,
bresp: bresp,
buser: wra.awuser}; // XXX This requires that Wd_AW_User == Wd_B_User
slave_xactor.master.b.put(wrr);
AXI4_BFlit#(Wd_SId, 0) wrr = AXI4_BFlit {bid: wra.awid,
bresp: bresp,
buser: 0};
slavePortShim.master.b.put(wrr);
if (verbosity > 0) begin
$display ("%0d: Boot_ROM.rl_process_wr_req; ignoring all writes", cur_cycle);
@@ -206,14 +209,13 @@ module mkBoot_ROM (Boot_ROM_IFC);
rg_addr_base <= addr_base;
rg_addr_lim <= addr_lim;
rg_module_ready <= True;
slave_xactor.clear;
if (verbosity > 0) begin
$display ("%0d: Boot_ROM.set_addr_map: base 0x%0h lim 0x%0h", cur_cycle, addr_base, addr_lim);
end
endmethod
// Main Fabric Reqs/Rsps
interface slave = slave_xactor.slaveSynth;
interface slave = slavePortShim.slave;
endmodule
// ================================================================

34
src_Testbench/SoC/Mem_Controller.bsv
View File

@@ -207,8 +207,8 @@ interface Mem_Controller_IFC;
method Action set_addr_map (Fabric_Addr addr_base, Fabric_Addr addr_lim);
// Main Fabric Reqs/Rsps
interface AXI4_Slave_Synth #(Wd_SId, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User, Wd_AR_User, Wd_R_User) slave;
interface AXI4_Slave #(Wd_SId, Wd_Addr, Wd_Data, 0, 0, 0, 0, 0)
slave;
// To raw memory (outside the SoC)
interface MemoryClient #(Bits_per_Raw_Mem_Addr, Bits_per_Raw_Mem_Word) to_raw_mem;
@@ -269,9 +269,7 @@ module mkMem_Controller (Mem_Controller_IFC);
FIFOF #(Bit #(0)) f_reset_rsps <- mkFIFOF;
// Communication with fabric
AXI4_Slave_Width_Xactor#(Wd_SId, Wd_Addr, Wd_Data_Periph, Wd_Data,
Wd_AW_User_Periph, Wd_W_User_Periph, Wd_B_User_Periph, Wd_AR_User_Periph, Wd_R_User_Periph,
Wd_AW_User, Wd_W_User, Wd_B_User, Wd_AR_User, Wd_R_User) slave_xactor <- mkAXI4_Slave_Zeroing_Xactor;
let slavePortShim <- mkAXI4ShimFF;
// Requests merged from the (WrA, WrD) and RdA channels
FIFOF #(Req) f_reqs <- mkPipelineFIFOF;
@@ -304,7 +302,7 @@ module mkMem_Controller (Mem_Controller_IFC);
function Action fa_reset_actions;
action
slave_xactor.clear;
slavePortShim.clear;
f_raw_mem_reqs.clear;
f_raw_mem_rsps.clear;
rg_status <= 0;
@@ -345,7 +343,7 @@ module mkMem_Controller (Mem_Controller_IFC);
// Merge requests into a single queue, prioritizing reads over writes
rule rl_merge_rd_req;
let rda <- get(slave_xactor.master.ar);
let rda <- get(slavePortShim.master.ar);
let req = Req {req_op: REQ_OP_RD,
id: rda.arid,
addr: rda.araddr,
@@ -370,8 +368,8 @@ module mkMem_Controller (Mem_Controller_IFC);
(* descending_urgency = "rl_merge_rd_req, rl_merge_wr_req" *)
rule rl_merge_wr_req;
let wra <- get(slave_xactor.master.aw);
let wrd <- get(slave_xactor.master.w);
let wra <- get(slavePortShim.master.aw);
let wrd <- get(slavePortShim.master.w);
let req = Req {req_op: REQ_OP_WR,
id: wra.awid,
addr: wra.awaddr,
@@ -504,8 +502,8 @@ module mkMem_Controller (Mem_Controller_IFC);
rdata: rdata,
rresp: OKAY,
rlast: True,
ruser: f_reqs.first.user}; // XXX This requires that Wd_AR_User == Wd_R_User
slave_xactor.master.r.put(rdr);
ruser: 0'b0};
slavePortShim.master.r.put(rdr);
f_reqs.deq;
if (cfg_verbosity > 1) begin
@@ -546,8 +544,8 @@ module mkMem_Controller (Mem_Controller_IFC);
let wrr = AXI4_BFlit {bid: f_reqs.first.id,
bresp: OKAY,
buser: f_reqs.first.user}; // XXX This requires that Wd_AW_User == Wd_B_User
slave_xactor.master.b.put(wrr);
buser: 0'b0};
slavePortShim.master.b.put(wrr);
f_reqs.deq;
if (cfg_verbosity > 1) begin
@@ -616,8 +614,8 @@ module mkMem_Controller (Mem_Controller_IFC);
rdata: rdata, // for debugging only
rresp: SLVERR,
rlast: True,
ruser: f_reqs.first.user}; // XXX This requires that Wd_AR_User == Wd_R_User
slave_xactor.master.r.put(rdr);
ruser: 0'b0};
slavePortShim.master.r.put(rdr);
f_reqs.deq;
$write ("%0d: ERROR: Mem_Controller:", cur_cycle);
@@ -635,8 +633,8 @@ module mkMem_Controller (Mem_Controller_IFC);
&& (f_reqs.first.req_op == REQ_OP_WR));
let wrr = AXI4_BFlit {bid: f_reqs.first.id,
bresp: SLVERR,
buser: f_reqs.first.user}; // XXX This requires that Wd_AW_User == Wd_B_User
slave_xactor.master.b.put(wrr);
buser: 0'b0};
slavePortShim.master.b.put(wrr);
f_reqs.deq;
$write ("%0d: ERROR: Mem_Controller:", cur_cycle);
@@ -671,7 +669,7 @@ module mkMem_Controller (Mem_Controller_IFC);
endmethod
// Main Fabric Reqs/Rsps
interface slave = slave_xactor.slaveSynth;
interface slave = slavePortShim.slave;
// To raw memory (outside the SoC)
interface to_raw_mem = toGPClient (f_raw_mem_reqs, f_raw_mem_rsps);

42
src_Testbench/SoC/SoC_Top.bsv
View File

@@ -153,16 +153,14 @@ module mkSoC_Top #(Reset dm_power_on_reset)
// SoC Boot ROM
Boot_ROM_IFC boot_rom <- mkBoot_ROM;
// AXI4 Deburster in front of Boot_ROM
AXI4_Shim#(Wd_SId, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User, Wd_AR_User, Wd_R_User)
boot_rom_axi4_deburster <- mkBurstToNoBurst;
AXI4_Shim#(Wd_SId, Wd_Addr, Wd_Data, 0, 0, 0, 0, 0)
boot_rom_axi4_deburster <- mkBurstToNoBurst;
// SoC Memory
Mem_Controller_IFC mem0_controller <- mkMem_Controller;
// AXI4 Deburster in front of SoC Memory
AXI4_Shim#(Wd_SId, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User, Wd_AR_User, Wd_R_User)
mem0_controller_axi4_deburster <- mkBurstToNoBurst;
AXI4_Shim#(Wd_SId, Wd_Addr, Wd_Data, 0, 0, 0, 0, 0)
mem0_controller_axi4_deburster <- mkBurstToNoBurst;
// SoC IPs
UART_IFC uart0 <- mkUART;
@@ -176,9 +174,9 @@ module mkSoC_Top #(Reset dm_power_on_reset)
// SoC fabric master connections
// Note: see 'SoC_Map' for 'master_num' definitions
Vector#(Num_Masters, AXI4_Master_Synth #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
0, 0, 0, 0, 0))
master_vector = newVector;
Vector#(Num_Masters, AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
0, 0, 0, 0, 0))
master_vector = newVector;
// CPU IMem master to fabric
master_vector[imem_master_num] = corew.cpu_imem_master;
@@ -190,30 +188,28 @@ module mkSoC_Top #(Reset dm_power_on_reset)
// SoC fabric slave connections
// Note: see 'SoC_Map' for 'slave_num' definitions
Vector#(Num_Slaves, AXI4_Slave_Synth #(Wd_SId, Wd_Addr, Wd_Data,
0, 0, 0, 0, 0))
slave_vector = newVector;
Vector#(Num_Slaves, Range#(Wd_Addr)) route_vector = newVector;
Vector#(Num_Slaves, AXI4_Slave #(Wd_SId, Wd_Addr, Wd_Data,
0, 0, 0, 0, 0))
slave_vector = newVector;
Vector#(Num_Slaves, Range#(Wd_Addr)) route_vector = newVector;
// Fabric to Boot ROM
let br <- fromAXI4_Slave_Synth(boot_rom.slave);
mkConnection(boot_rom_axi4_deburster.master, br);
slave_vector[boot_rom_slave_num] <- toAXI4_Slave_Synth(zeroSlaveUserFields(boot_rom_axi4_deburster.slave));
mkConnection(boot_rom_axi4_deburster.master, boot_rom.slave);
slave_vector[boot_rom_slave_num] = boot_rom_axi4_deburster.slave;
route_vector[boot_rom_slave_num] = soc_map.m_boot_rom_addr_range;
// Fabric to Mem Controller
let mem <- fromAXI4_Slave_Synth(mem0_controller.slave);
mkConnection(mem0_controller_axi4_deburster.master, mem);
slave_vector[mem0_controller_slave_num] <- toAXI4_Slave_Synth(zeroSlaveUserFields(mem0_controller_axi4_deburster.slave));
mkConnection(mem0_controller_axi4_deburster.master, mem0_controller.slave);
slave_vector[mem0_controller_slave_num] = mem0_controller_axi4_deburster.slave;
route_vector[mem0_controller_slave_num] = soc_map.m_mem0_controller_addr_range;
// Fabric to UART0
slave_vector[uart0_slave_num] <- toAXI4_Slave_Synth(zeroSlaveUserFields(uart0.slave));
slave_vector[uart0_slave_num] = zeroSlaveUserFields(uart0.slave);
route_vector[uart0_slave_num] = soc_map.m_uart0_addr_range;
`ifdef INCLUDE_ACCEL0
// Fabric to accel0
slave_vector[accel0_slave_num] <- liftAXI4_Slave_Synth(zeroSlaveUserFields, accel0.slave);
slave_vector[accel0_slave_num] = zeroSlaveUserFields (accel0.slave);
route_vector[accel0_slave_num] = soc_map.m_accel0_addr_range;
`endif
@@ -225,8 +221,8 @@ module mkSoC_Top #(Reset dm_power_on_reset)
`endif
// SoC Fabric
let bus <- mkAXI4Bus_Synth (routeFromMappingTable(route_vector),
master_vector, slave_vector);
let bus <- mkAXI4Bus (routeFromMappingTable(route_vector),
master_vector, slave_vector);
// ----------------
// Connect interrupt sources for CPU external interrupt request inputs.