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Use order-only prerequisites for directories

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Hopefully this stops .depends.mk from being generated more than
necessary, as presumably the fact that compile and simulator both add
new files to build_dir (and Verilog_RTL for Verilator) causes the
timestamp to change and thus make to think .depends.mk is stale.
This commit is contained in:
Jessica Clarke
2021-02-28 04:14:54 +00:00
parent e1060ac43d
commit 9dc27542f3
3 changed files with 6 additions and 6 deletions
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4
builds/Resources/Include_bluesim.mk
View File

@@ -15,7 +15,7 @@ build_dir:
ifeq (,$(filter clean full_clean,$(MAKECMDGOALS)))
include .depends.mk
.depends.mk: build_dir
.depends.mk: | build_dir
if ! bluetcl -exec makedepend -elab -sim $(TMP_DIRS) $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) -o $@ $(TOPFILE); then rm -f $@ && false; fi
endif
@@ -24,7 +24,7 @@ endif
bsc -elab -sim $(TMP_DIRS) $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) $<
.PHONY: compile
compile: build_dir build_dir/Top_HW_Side.bo
compile: build_dir/Top_HW_Side.bo | build_dir
# @echo "INFO: Re-compiling Core (CPU, Caches)"
# bsc -u -elab -sim $(TMP_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) $(TOPFILE)
# @echo "INFO: Re-compiled Core (CPU, Caches)"

4
builds/Resources/Include_verilator.mk
View File

@@ -18,7 +18,7 @@ Verilog_RTL:
ifeq (,$(filter clean full_clean,$(MAKECMDGOALS)))
include .depends.mk
.depends.mk: build_dir Verilog_RTL
.depends.mk: | build_dir Verilog_RTL
if ! bluetcl -exec makedepend -verilog -elab $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) -o $@ $(TOPFILE); then rm -f $@ && false; fi
endif
@@ -27,7 +27,7 @@ endif
bsc -verilog -elab $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) $<
.PHONY: compile
compile: build_dir Verilog_RTL build_dir/Top_HW_Side.bo
compile: build_dir/Top_HW_Side.bo | build_dir Verilog_RTL
#Verilog_RTL/mkTop_HW_Side.v: build_dir Verilog_RTL /tmp/src_dir $(VERILOG_SUB_MODULES)
#Verilog_RTL/mkTop_HW_Side.v: $(TOPFILE) build_dir/Top_HW_Side.bo build_dir Verilog_RTL
# @echo "INFO: Verilog RTL generation ..."

4
src_SSITH_P3/Makefile
View File

@@ -115,13 +115,13 @@ Verilog_RTL_sim:
mkdir -p $@
.PHONY: compile_synth
compile_synth: build_dir_synth Verilog_RTL
compile_synth: | build_dir_synth Verilog_RTL
@echo "INFO: Generating RTL into Verilog_RTL for synthesis ..."
bsc -u -elab -verilog -vdir Verilog_RTL $(BUILD_DIRS_SYNTH) $(BSC_COMPILATION_FLAGS) $(SYNTH_BSC_OPTIONS) $(BSC_PATH) $(TOPFILE)
@echo "INFO: Generated Synth RTL into Verilog_RTL"
.PHONY: compile_sim
compile_sim: build_dir_sim Verilog_RTL_sim
compile_sim: | build_dir_sim Verilog_RTL_sim
@echo "INFO: Generating RTL into Verilog_RTL_sim for simulation ..."
bsc -u -elab -verilog -vdir Verilog_RTL_sim $(BUILD_DIRS_SIM) $(BSC_COMPILATION_FLAGS) $(SIM_BSC_OPTIONS) $(BSC_PATH) $(TOPFILE)