Cheri-research/Toooba
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This commit is contained in:
Akilan Selvacoumar
2026-01-25 14:24:20 +00:00
parent f2cc45d169
commit 9f7aa79b99
2 changed files with 35 additions and 37 deletions
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4
builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile
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@@ -8,9 +8,9 @@ ARCH ?= RV64ACDFIMSUxCHERI
BSC_COMPILATION_FLAGS += -verbose
# Default ISA test
# TEST ?= rv64ui-p-add
TEST ?= rv64ui-p-add
# TEST ?= rv64um-v-mulw
TEST ?= Page
# TEST ?= Page
# TEST ?= PageReadWrite
# TEST ?= CheriPage

68
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
View File

@@ -683,16 +683,16 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
// Assuming physcial address is virtual address just for testing
let paddr = getAddr(lol.vaddr);
// These are just assumtions for testing
let expCause = False;
// let expCause = dTlb.Invalid;
let allowCapPTE = True;
if(verbose) $display("%t : [doFinishMem] ", $time, fshow(regToExe));
// Moved to the next stage
// let shiftBE = DataMemAccess(x.shiftBEData);
// if (x.origBE == TagMemAccess) begin
// shiftBE = TagMemAccess;
// end
let shiftBE = DataMemAccess(lol.shiftBEData);
if (lol.origBE == TagMemAccess) begin
shiftBE = TagMemAccess;
end
CapPipe ddc = cast(inIfc.scaprf_rd(scrAddrDDC));
@@ -731,14 +731,11 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
// (done) tag
// (done) ldstq_tag
// (done) shiftedBE
let shiftBE = DataMemAccess(lol.shiftBEData);
if (lol.origBE == TagMemAccess) begin
shiftBE = TagMemAccess;
end
Maybe#(Trap) cause = Invalid;
// if (expCause matches tagged Valid .c) cause = Valid(Exception(c));
// if(verbose) $display("%t : [doFinishMem] ", $time, fshow(dTlbResp));
$display("Bypassing TLB");
// if(isValid(cause) && verbose) $display(" [doFinishMem - dTlb response] PAGEFAULT!");
@@ -749,18 +746,19 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
// store_data = tlbresp.store_data;
// store_data_BE = tlbresp.store_data_BE;
// `endif
let misaligned = memAddrMisaligned(getAddr(lol.vaddr), lol.origBE);
// check misalignment
// if(!isValid(cause) && x.misaligned) begin
// case(x.mem_func)
// Ld, Lr: begin
// cause = Valid(Exception(excLoadAddrMisaligned));
// end
// default: begin
// cause = Valid(Exception(excStoreAddrMisaligned));
// end
// endcase
// end
if(!isValid(cause) && misaligned) begin
case(lol.mem_func)
Ld, Lr: begin
cause = Valid(Exception(excLoadAddrMisaligned));
end
default: begin
cause = Valid(Exception(excStoreAddrMisaligned));
end
endcase
end
// `ifdef RVFI_DII
// // TestRIG expects us throw an access fault for any memory access outside of a 8 MiB memory at 0x8000000.
@@ -779,16 +777,16 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
// check if addr is MMIO (only valid in case of no page fault)
Bool isMMIO = inIfc.isMMIOAddr(paddr);
// raise access fault in case of MMIO Lr/Sc
// if(!isValid(cause) && isMMIO) begin
// case(lol.mem_func)
// Lr: begin
// cause = Valid(Exception(excLoadAccessFault));
// end
// Sc: begin
// cause = Valid(Exception(excStoreAccessFault));
// end
// endcase
// end
if(!isValid(cause) && isMMIO) begin
case(lol.mem_func)
Lr: begin
cause = Valid(Exception(excLoadAccessFault));
end
Sc: begin
cause = Valid(Exception(excStoreAccessFault));
end
endcase
end
// update ROB (access at commit and non-mmio st done can only be true
// when there is no exceptio)
@@ -802,17 +800,17 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
: (check.check_high < check.authority_top ))))
capException = Valid(CSR_XCapCause{cheri_exc_reg: check.authority_idx, cheri_exc_code: cheriExcLengthViolation});
end
// if (capException matches tagged Valid .c) cause = Valid(CapException(c));
// Bool access_at_commit = !isValid(cause) && (isMMIO || isLrScAmo);
Bool access_at_commit = True;
// Bool non_mmio_st_done = !isValid(cause) && !isMMIO && lol.mem_func == St;
Bool non_mmio_st_done = !isMMIO && lol.mem_func == St;
if (capException matches tagged Valid .c) cause = Valid(CapException(c));
Bool access_at_commit = !isValid(cause) && (isMMIO || isLrScAmo);
// Bool access_at_commit = True;
Bool non_mmio_st_done = !isValid(cause) && !isMMIO && lol.mem_func == St;
// Bool non_mmio_st_done = !isMMIO && lol.mem_func == St;
inIfc.rob_setExecuted_doFinishMem(lol.tag, getAddr(lol.vaddr),
// `ifdef INCLUDE_TANDEM_VERIF
// store_data, store_data_BE,
// `endif
access_at_commit, non_mmio_st_done
// `ifdef RVFI
`ifdef RVFI
// , ExtraTraceBundle{
// regWriteData: memData[pack(tlbresp.ldstq_tag)],
// memByteEn: unpack(truncate(pack(tlbresp.shiftedBE.DataMemAccess) >> getAddr(tlbresp.vaddr)[3:0]))