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Set verbosity to 0 in TV_Encode and Trace_Data2_to_Trace_Data

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Updated src_SSITH_P3_sim SoC_Map
This commit is contained in:
Niraj N Sharma
2020-01-30 13:39:54 -05:00
parent f89ed020d8
commit a0a4093088
7 changed files with 44257 additions and 48855 deletions
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2
src_Core/Core/TV_Encode.bsv
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@@ -62,7 +62,7 @@ endinterface
(* synthesize *)
module mkTV_Encode (TV_Encode_IFC);
Integer verbosity = 1; // For debugging
Integer verbosity = 0; // For debugging
Reg #(Bool) rg_reset_done <- mkReg (False);

2
src_Core/Core/Trace_Data2_to_Trace_Data.bsv
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@@ -47,7 +47,7 @@ endinterface
module mkTrace_Data2_to_Trace_Data (Trace_Data2_to_Trace_Data_IFC);
Integer verbosity = 1; // for debugging
Integer verbosity = 0; // for debugging
// Input stream
FIFOF #(Trace_Data2) f_in <- mkFIFOF;

4707
src_SSITH_P3_sim/Verilog_RTL/mkCoreW.v
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File diff suppressed because it is too large Load Diff

34
src_SSITH_P3_sim/Verilog_RTL/mkP3_Core.v
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@@ -899,7 +899,7 @@ module mkP3_Core(CLK,
// inputs to muxes for submodule ports
wire [33 : 0] MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1,
MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2,
MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1,
MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2,
MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1,
MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2;
wire [1 : 0] MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2;
@@ -1458,31 +1458,31 @@ module mkP3_Core(CLK,
// inputs to muxes for submodule ports
assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_1 =
WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 ;
assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2 =
WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr &&
bus_dmi_rsp_fifof_cntr_r == 2'd0 ;
assign MUX_bus_dmi_rsp_fifof_q_0$write_1__SEL_2 =
WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 ;
assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1 =
WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 ;
assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 =
WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr &&
bus_dmi_rsp_fifof_cntr_r == 2'd1 ;
assign MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 =
WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 ;
assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1 =
WILL_FIRE_RL_rl_dmi_req_cpu &&
bus_dmi_req_fifof$D_OUT[1:0] != 2'd1 ;
assign MUX_bus_dmi_rsp_fifof_cntr_r$write_1__VAL_2 =
bus_dmi_rsp_fifof_cntr_r + 2'd1 ;
assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 =
(bus_dmi_rsp_fifof_cntr_r == 2'd1) ?
MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 :
bus_dmi_rsp_fifof_q_1 ;
assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 =
MUX_bus_dmi_rsp_fifof_x_wire$wset_1__SEL_1 ?
MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1 :
MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_2 ;
assign MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1 =
assign MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 =
(bus_dmi_rsp_fifof_cntr_r == 2'd1) ?
MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 :
bus_dmi_rsp_fifof_q_1 ;
assign MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2 =
(bus_dmi_rsp_fifof_cntr_r == 2'd2) ?
MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 :
MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 :
34'd0 ;
assign MUX_bus_dmi_rsp_fifof_x_wire$wset_1__VAL_1 =
{ 32'hAAAAAAAA,
@@ -1530,25 +1530,25 @@ module mkP3_Core(CLK,
endcase
end
assign bus_dmi_rsp_fifof_q_0$EN =
WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 ||
WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr &&
bus_dmi_rsp_fifof_cntr_r == 2'd0 ||
WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo3 ||
WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ;
// register bus_dmi_rsp_fifof_q_1
always@(MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1 or
MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1 or
MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1 or
MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2 or
MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2 or
MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2 or
WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_1:
bus_dmi_rsp_fifof_q_1$D_IN =
MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_1;
MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_1;
MUX_bus_dmi_rsp_fifof_q_1$write_1__SEL_2:
bus_dmi_rsp_fifof_q_1$D_IN =
MUX_bus_dmi_rsp_fifof_q_0$write_1__VAL_2;
MUX_bus_dmi_rsp_fifof_q_1$write_1__VAL_2;
WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr:
bus_dmi_rsp_fifof_q_1$D_IN = 34'd0;
default: bus_dmi_rsp_fifof_q_1$D_IN =
@@ -1556,9 +1556,9 @@ module mkP3_Core(CLK,
endcase
end
assign bus_dmi_rsp_fifof_q_1$EN =
WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 ||
WILL_FIRE_RL_bus_dmi_rsp_fifof_incCtr &&
bus_dmi_rsp_fifof_cntr_r == 2'd1 ||
WILL_FIRE_RL_bus_dmi_rsp_fifof_both && _dfoo1 ||
WILL_FIRE_RL_bus_dmi_rsp_fifof_decCtr ;
// register rg_once

70
src_SSITH_P3_sim/Verilog_RTL/mkSoC_Map.v
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@@ -317,7 +317,11 @@ module mkSoC_Map(CLK,
wire m_is_IO_addr, m_is_mem_addr, m_is_near_mem_IO_addr;
// remaining internal signals
wire m_is_IO_addr_addr_ULT_0x70000000___d35;
wire NOT_m_is_IO_addr_addr_ULT_0xC000000_AND_m_is_I_ETC___d37,
NOT_m_is_IO_addr_addr_ULT_0xC000000_AND_m_is_I_ETC___d82,
m_is_IO_addr_addr_ULT_0x30000000___d80,
m_is_IO_addr_addr_ULT_0x70000000___d35,
m_is_IO_addr_addr_ULT_1073741824___d13;
// value method m_plic_addr_base
assign m_plic_addr_base = 64'h000000000C000000 ;
@@ -341,10 +345,10 @@ module mkSoC_Map(CLK,
assign m_flash_mem_addr_base = 64'h0000000040000000 ;
// value method m_flash_mem_addr_size
assign m_flash_mem_addr_size = 64'h0000000000010000 ;
assign m_flash_mem_addr_size = 64'h0000000008000000 ;
// value method m_flash_mem_addr_lim
assign m_flash_mem_addr_lim = 64'd1073807360 ;
assign m_flash_mem_addr_lim = 64'd1207959552 ;
// value method m_ethernet_0_addr_base
assign m_ethernet_0_addr_base = 64'h0000000062100000 ;
@@ -425,24 +429,9 @@ module mkSoC_Map(CLK,
// value method m_is_IO_addr
assign m_is_IO_addr =
m_is_IO_addr_addr >= 64'h000000000C000000 &&
m_is_IO_addr_addr < 64'd205520896 ||
m_is_IO_addr_addr >= 64'h0000000010000000 &&
m_is_IO_addr_addr < 64'd268500992 ||
m_is_IO_addr_addr >= 64'h0000000040000000 &&
m_is_IO_addr_addr < 64'd1073807360 ||
m_is_IO_addr_addr >= 64'h0000000062100000 &&
m_is_IO_addr_addr < 64'd1645477888 ||
m_is_IO_addr_addr >= 64'h0000000062200000 &&
m_is_IO_addr_addr < 64'd1646329856 ||
m_is_IO_addr_addr >= 64'h0000000062300000 &&
m_is_IO_addr_addr < 64'd1647316992 ||
m_is_IO_addr_addr >= 64'h000000006FFF0000 &&
m_is_IO_addr_addr_ULT_0x70000000___d35 ||
!m_is_IO_addr_addr_ULT_0x70000000___d35 &&
m_is_IO_addr_addr < 64'd1879052288 ||
m_is_IO_addr_addr >= 64'h0000000080000000 &&
m_is_IO_addr_addr < 64'h00000000C0000000 ;
NOT_m_is_IO_addr_addr_ULT_0xC000000_AND_m_is_I_ETC___d82 ||
!m_is_IO_addr_addr_ULT_0x30000000___d80 &&
m_is_IO_addr_addr_ULT_1073741824___d13 ;
// value method m_is_near_mem_IO_addr
assign m_is_near_mem_IO_addr =
@@ -459,7 +448,46 @@ module mkSoC_Map(CLK,
assign m_nmivec_reset_value = 64'hAAAAAAAAAAAAAAAA ;
// remaining internal signals
assign NOT_m_is_IO_addr_addr_ULT_0xC000000_AND_m_is_I_ETC___d37 =
m_is_IO_addr_addr >= 64'h000000000C000000 &&
m_is_IO_addr_addr < 64'd205520896 ||
m_is_IO_addr_addr >= 64'h0000000010000000 &&
m_is_IO_addr_addr < 64'd268500992 ||
!m_is_IO_addr_addr_ULT_1073741824___d13 &&
m_is_IO_addr_addr < 64'd1207959552 ||
m_is_IO_addr_addr >= 64'h0000000062100000 &&
m_is_IO_addr_addr < 64'd1645477888 ||
m_is_IO_addr_addr >= 64'h0000000062200000 &&
m_is_IO_addr_addr < 64'd1646329856 ||
m_is_IO_addr_addr >= 64'h0000000062300000 &&
m_is_IO_addr_addr < 64'd1647316992 ||
m_is_IO_addr_addr >= 64'h000000006FFF0000 &&
m_is_IO_addr_addr_ULT_0x70000000___d35 ;
assign NOT_m_is_IO_addr_addr_ULT_0xC000000_AND_m_is_I_ETC___d82 =
NOT_m_is_IO_addr_addr_ULT_0xC000000_AND_m_is_I_ETC___d37 ||
!m_is_IO_addr_addr_ULT_0x70000000___d35 &&
m_is_IO_addr_addr < 64'd1879052288 ||
m_is_IO_addr_addr >= 64'h0000000080000000 &&
m_is_IO_addr_addr < 64'h00000000C0000000 ||
m_is_IO_addr_addr >= 64'h0000000062400000 &&
m_is_IO_addr_addr < 64'd1648365568 ||
m_is_IO_addr_addr >= 64'h0000000062310000 &&
m_is_IO_addr_addr < 64'd1647382528 ||
m_is_IO_addr_addr >= 64'h0000000062320000 &&
m_is_IO_addr_addr < 64'd1647448064 ||
m_is_IO_addr_addr >= 64'h0000000062360000 &&
m_is_IO_addr_addr < 64'd1647710208 ||
m_is_IO_addr_addr >= 64'h0000000062330000 &&
m_is_IO_addr_addr < 64'd1647513600 ||
m_is_IO_addr_addr >= 64'h0000000062370000 &&
m_is_IO_addr_addr < 64'd1647775744 ||
m_is_IO_addr_addr >= 64'h0000000020000000 &&
m_is_IO_addr_addr_ULT_0x30000000___d80 ;
assign m_is_IO_addr_addr_ULT_0x30000000___d80 =
m_is_IO_addr_addr < 64'h0000000030000000 ;
assign m_is_IO_addr_addr_ULT_0x70000000___d35 =
m_is_IO_addr_addr < 64'h0000000070000000 ;
assign m_is_IO_addr_addr_ULT_1073741824___d13 =
m_is_IO_addr_addr < 64'd1073741824 ;
endmodule // mkSoC_Map

88213
src_SSITH_P3_sim/Verilog_RTL/mkTV_Encode.v
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File diff suppressed because it is too large Load Diff

84
src_SSITH_P3_sim/src_BSV/SoC_Map.bsv
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@@ -75,6 +75,12 @@ SoC_Map_Struct {
pc_reset_value: 'h_7000_0000 // = boot_rom_addr_base
};
// ================================================================
function Bool addr_function(Fabric_Addr base, Fabric_Addr size, Fabric_Addr addr);
return (base <= addr) && (addr < (base + size));
endfunction
// ================================================================
// Interface and module for the address map
@@ -87,22 +93,10 @@ interface SoC_Map_IFC;
(* always_ready *) method Fabric_Addr m_near_mem_io_addr_size;
(* always_ready *) method Fabric_Addr m_near_mem_io_addr_lim;
/* REMOVED?
(* always_ready *) method Fabric_Addr m_pcie_ecam_slave_bridge_addr_base;
(* always_ready *) method Fabric_Addr m_pcie_ecam_slave_bridge_addr_size;
(* always_ready *) method Fabric_Addr m_pcie_ecam_slave_bridge_addr_lim;
*/
(* always_ready *) method Fabric_Addr m_flash_mem_addr_base;
(* always_ready *) method Fabric_Addr m_flash_mem_addr_size;
(* always_ready *) method Fabric_Addr m_flash_mem_addr_lim;
/* REMOVED?
(* always_ready *) method Fabric_Addr m_pcie_block_registers_addr_base;
(* always_ready *) method Fabric_Addr m_pcie_block_registers_addr_size;
(* always_ready *) method Fabric_Addr m_pcie_block_registers_addr_lim;
*/
(* always_ready *) method Fabric_Addr m_ethernet_0_addr_base;
(* always_ready *) method Fabric_Addr m_ethernet_0_addr_size;
(* always_ready *) method Fabric_Addr m_ethernet_0_addr_lim;
@@ -176,45 +170,17 @@ module mkSoC_Map (SoC_Map_IFC);
return ((near_mem_io_addr_base <= addr) && (addr < near_mem_io_addr_lim));
endfunction
// ----------------------------------------------------------------
// PCIE_ECAM_SLAVE_BRIDGE
/* REMOVED?
Fabric_Addr pcie_ecam_slave_bridge_addr_base = 'h_2000_0000;
Fabric_Addr pcie_ecam_slave_bridge_addr_size = 'h_2000_0000; // 512M
Fabric_Addr pcie_ecam_slave_bridge_addr_lim = ( pcie_ecam_slave_bridge_addr_base
+ pcie_ecam_slave_bridge_addr_size);
function Bool fn_is_pcie_ecam_slave_bridge_addr (Fabric_Addr addr);
return ((pcie_ecam_slave_bridge_addr_base <= addr) && (addr < pcie_ecam_slave_bridge_addr_lim));
endfunction
*/
// ----------------------------------------------------------------
// Flash Mem
Fabric_Addr flash_mem_addr_base = 'h_4000_0000;
Fabric_Addr flash_mem_addr_size = 'h_0001_0000; // 64K
Fabric_Addr flash_mem_addr_size = 'h_0800_0000; // 128M
Fabric_Addr flash_mem_addr_lim = flash_mem_addr_base + flash_mem_addr_size;
function Bool fn_is_flash_mem_addr (Fabric_Addr addr);
return ((flash_mem_addr_base <= addr) && (addr < flash_mem_addr_lim));
endfunction
// ----------------------------------------------------------------
// PCIe Block Registers
/* REMOVED?
Fabric_Addr pcie_block_registers_addr_base = 'h_6000_0000;
Fabric_Addr pcie_block_registers_addr_size = 'h_0001_0000; // 64K
Fabric_Addr pcie_block_registers_addr_lim = ( pcie_block_registers_addr_base
+ pcie_block_registers_addr_size);
function Bool fn_is_pcie_block_registers_addr (Fabric_Addr addr);
return ((pcie_block_registers_addr_base <= addr) && (addr < pcie_block_registers_addr_lim));
endfunction
*/
// ----------------------------------------------------------------
// Ethernet 0
@@ -292,6 +258,19 @@ module mkSoC_Map (SoC_Map_IFC);
return ((ddr4_0_cached_addr_base <= addr) && (addr < ddr4_0_cached_addr_lim));
endfunction
// ----------------------------------------------------------------
function fn_is_flash_regs_addr = addr_function('h6240_0000, 'h1000);
function fn_is_uart1_addr = addr_function('h6230_0000, 'h1000);
function fn_is_i2c_addr = addr_function('h6231_0000, 'h1000);
function fn_is_spi_addr = addr_function('h6232_0000, 'h1000);
function fn_is_uart2_addr = addr_function('h6236_0000, 'h1000);
function fn_is_gpio1_addr = addr_function('h6233_0000, 'h1000);
function fn_is_gpio2_addr = addr_function('h6237_0000, 'h1000);
function fn_is_xdma_control = addr_function('h2000_0000, 'h1000_0000);
function fn_is_xdma_ecam = addr_function('h3000_0000, 'h1000_0000);
// ----------------------------------------------------------------
// Memory address predicate
// Identifies memory addresses in the Fabric.
@@ -310,15 +289,22 @@ module mkSoC_Map (SoC_Map_IFC);
function Bool fn_is_IO_addr (Fabric_Addr addr);
return ( fn_is_plic_addr (addr)
|| fn_is_near_mem_io_addr (addr)
// || fn_is_pcie_ecam_slave_bridge_addr (addr)
|| fn_is_flash_mem_addr (addr)
// || fn_is_pcie_block_registers_addr (addr)
|| fn_is_ethernet_0_addr (addr)
|| fn_is_dma_0_addr (addr)
|| fn_is_uart16550_0_addr (addr)
|| fn_is_gpio_0_addr (addr)
|| fn_is_boot_rom_addr (addr)
|| fn_is_ddr4_0_uncached_addr (addr)
|| fn_is_flash_regs_addr (addr)
|| fn_is_uart1_addr (addr)
|| fn_is_i2c_addr (addr)
|| fn_is_spi_addr (addr)
|| fn_is_uart2_addr (addr)
|| fn_is_gpio1_addr (addr)
|| fn_is_gpio2_addr (addr)
|| fn_is_xdma_control (addr)
|| fn_is_xdma_ecam (addr)
);
endfunction
@@ -340,22 +326,10 @@ module mkSoC_Map (SoC_Map_IFC);
method Fabric_Addr m_near_mem_io_addr_size = near_mem_io_addr_size;
method Fabric_Addr m_near_mem_io_addr_lim = near_mem_io_addr_lim;
/* REMOVED?
method Fabric_Addr m_pcie_ecam_slave_bridge_addr_base = pcie_ecam_slave_bridge_addr_base;
method Fabric_Addr m_pcie_ecam_slave_bridge_addr_size = pcie_ecam_slave_bridge_addr_size;
method Fabric_Addr m_pcie_ecam_slave_bridge_addr_lim = pcie_ecam_slave_bridge_addr_lim;
*/
method Fabric_Addr m_flash_mem_addr_base = flash_mem_addr_base;
method Fabric_Addr m_flash_mem_addr_size = flash_mem_addr_size;
method Fabric_Addr m_flash_mem_addr_lim = flash_mem_addr_lim;
/* REMOVED?
method Fabric_Addr m_pcie_block_registers_addr_base = pcie_block_registers_addr_base;
method Fabric_Addr m_pcie_block_registers_addr_size = pcie_block_registers_addr_size;
method Fabric_Addr m_pcie_block_registers_addr_lim = pcie_block_registers_addr_lim;
*/
method Fabric_Addr m_ethernet_0_addr_base = ethernet_0_addr_base;
method Fabric_Addr m_ethernet_0_addr_size = ethernet_0_addr_size;
method Fabric_Addr m_ethernet_0_addr_lim = ethernet_0_addr_lim;