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added tlb bypass

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This commit is contained in:
Akilan Selvacoumar
2026-03-13 13:19:43 +00:00
parent 6fa2e4a36e
commit a0b8d07155
4 changed files with 142 additions and 105 deletions
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29
builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt
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@@ -51,10 +51,11 @@ instret:2 PC:0x1ffff0000000000000000000000001008 instr:0xf1402573 iType:Csr
[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
3340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
3350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000018, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
3360 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000018, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000000001000 o: 'h0000000000001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
3360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000018, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000000001000 o: 'h0000000000001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
Decoded delta = 0
DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000001018, write: False, capStore: False, potentialCapLoad: False }
3370 : [doFinishMem] DTlbResp { resp: <'h0000000000001018,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000001018, check_high: 'h00000000000001020, check_inclusive: True } }, specBits: 'h000 }
Received delta = 0
3370 : [doFinishMem] DTlbResp { resp: <'h0000000000001018,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000001018, check_high: 'h00000000000001020, check_inclusive: True } }, specBits: 'h000 }
[doDeqLdQ_MMIO_issue] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; MMIOCRq { addr: 'h0000000000001018, func: tagged Ld , byteEn: <V False False False False False False False False True True True True True True True True >, data: TaggedData { tag: , data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, loadTags: False }
[RFile] wr_ 3: r 43 <= 0000000020000000000000001fffff44000000
[doDeqLdQ_MMIO_deq] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080000000 > }; TaggedData { tag: False, data: <V 'h0000000080000000 'h0000000000000000 > }
@@ -93,25 +94,27 @@ instret:9 PC:0x1ffff000000000000000000008000000c instr:0x2052815b iType:Cap
instret:10 PC:0x1ffff0000000000000000000080000010 instr:0x000043a1 iType:Alu [doCommitNormalInst [1]] 1158
[RFile] wr_ 0: r 4c <= 0000014020000400100000001ffff804021000
[RFile] wr_ 1: r 4f <= 0000000000000000400000001fffff44000000
11590 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000050080001000 o: 'h0000050080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000050080001000 o: 'h0000050080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
11590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000050080001000 o: 'h0000050080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000050080001000 o: 'h0000050080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
Decoded delta = 10
DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001000, write: False, capStore: False, potentialCapLoad: False }
11590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
instret:11 PC:0x1ffff0000000000000000000080000012 instr:0x1071015b iType:Cap [doCommitNormalInst [0]] 1159
[RFile] wr_ 1: r 4d <= 0000014020000400000000001fffff44000000
11600 : [doFinishMem] DTlbResp { resp: <'h0000000080001000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001000, check_high: 'h00000000080001008, check_inclusive: True } }, specBits: 'h000 }
11600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080001000, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h801e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
11600 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
Received delta = 10
11600 : [doFinishMem] DTlbResp { resp: <'h0000000080001000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h000000a, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001000, check_high: 'h00000000080001008, check_inclusive: True } }, specBits: 'h000 }
11600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h000000008000100a, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h801e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
11600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
Decoded delta = 0
DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: False, potentialCapLoad: False }
11600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h801e }
11600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h000000008000100a, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h801e }
instret:12 PC:0x1ffff0000000000000000000080000016 instr:0x00a1115b iType:Cap [doCommitNormalInst [0]] 1160
11610 : [doFinishMem] DTlbResp { resp: <'h0000000000000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000000000, check_high: 'h00000000000000008, check_inclusive: True } }, specBits: 'h000 }
Received delta = 0
11610 : [doFinishMem] DTlbResp { resp: <'h0000000000000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000000000, check_high: 'h00000000000000008, check_inclusive: True } }, specBits: 'h000 }
11610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
11610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h801e }
11610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h000000008000100a, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h801e }
11610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
instret:13 PC:0x1ffff000000000000000000008000001a instr:0xfe210e5b iType:Cap [doCommitNormalInst [0]] 1161
11630 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h801e } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001000, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
11630 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h01, addr: 'h000000008000100a, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h801e } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h000000008000100a, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
@@ -136,18 +139,18 @@ instret:13 PC:0x1ffff000000000000000000008000001a instr:0xfe210e5b iType:Cap
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
12370 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001000, toState: E, child: , data: tagged Valid CLine { tag: <V False False False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > }, id: 'h0 }
12370 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h000000008000100a, toState: E, child: , data: tagged Valid CLine { tag: <V False False False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > }, id: 'h0 }
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
12380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: <V False False False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
12380 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
12380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h801e }
12380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h000000008000100a, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h801e }
12380 : [Ld resp] 'h01; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }
12380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
12390 : [doRespLdMem] 'h01; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
[RFile] wr_ 3: r 4e <= 0000000000000000000000001fffff44000000
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h0000000080001000, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h000000008000100a, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
instret:14 PC:0x1ffff000000000000000000008000001e instr:0x00006282 iType:Ld [doCommitNormalInst [0]] 1241
instret:15 PC:0x1ffff0000000000000000000080000020 instr:0x00004305 iType:Alu [doCommitNormalInst [1]] 1241

2
libs/cheri-cap-lib

Submodule libs/cheri-cap-lib updated: 3c6d203186...6120b13246

42
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
View File

@@ -124,6 +124,8 @@ typedef struct {
// result
ByteOrTagEn shiftedBE;
CapPipe vaddr; // virtual addr
Bit#(25) delta;
`ifdef INCLUDE_TANDEM_VERIF
// for those mem instrs that store data
Data store_data;
@@ -597,13 +599,11 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
});
endrule
rule doExeMem;
rule doExeAndDoMem;
regToExeQ.deq;
let regToExe = regToExeQ.first;
let x = regToExe.data;
// trollToExeQ.enq(regToExe);
// ==============================
if(verbose) $display("%t : [doExeMem] ", $time, fshow(regToExe));
if(verbose) $display("%t : [doExeAndDoMem] ", $time, fshow(regToExe));
let shiftBE = DataMemAccess(x.shiftBEData);
if (x.origBE == TagMemAccess) begin
@@ -618,6 +618,34 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
accessByteCount = fromInteger(valueOf(CacheUtils::CLineNumMemDataBytes));
end
// rule doExeMem;
// regToExeQ.deq;
// let regToExe = regToExeQ.first;
// let x = regToExe.data;
// // trollToExeQ.enq(regToExe);
// // ==============================
// if(verbose) $display("%t : [doExeMem] ", $time, fshow(regToExe));
// let shiftBE = DataMemAccess(x.shiftBEData);
// if (x.origBE == TagMemAccess) begin
// shiftBE = TagMemAccess;
// end
// CapPipe ddc = cast(inIfc.scaprf_rd(scrAddrDDC));
// // get size of the access
// Bit#(TAdd#(CacheUtils::LogCLineNumMemDataBytes,1)) accessByteCount = zeroExtend(pack(countOnes(pack(x.origBE.DataMemAccess))));
// if (x.origBE == TagMemAccess) begin
// accessByteCount = fromInteger(valueOf(CacheUtils::CLineNumMemDataBytes));
// end
// // Test delta value read from the pointer
// Bit#(25) delta = decodeDelta(x.vaddr);
// $display("Decoded delta = %0d", delta);
// x.vaddr = encodeDelta(x.vaddr, 0);
`ifdef KONATA
$display("KONATAE\t%0d\t%0d\t0\tMem2", cur_cycle, x.u_id);
$display("KONATAS\t%0d\t%0d\t0\tMem3", cur_cycle, x.u_id);
@@ -638,6 +666,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
ldstq_tag: x.ldstq_tag,
shiftedBE: shiftBE,
vaddr: x.vaddr,
delta: delta,
`ifdef INCLUDE_TANDEM_VERIF
store_data: x.rVal2,
store_data_BE: origBE,
@@ -665,6 +694,11 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
let dTlbResp = dTlb.procResp;
let x = dTlbResp.inst;
let {paddr, expCause, allowCapPTE} = dTlbResp.resp;
Bit#(25) delta = x.delta;
$display("Received delta = %0d", delta);
paddr = paddr + zeroExtend(delta);
// paddr = getAddr(lol.vaddr);
// expCause = False;
// allowCapPTE = True;

174
src_Core/RISCY_OOO/procs/lib/DTlb.bsv
View File

@@ -471,93 +471,93 @@ module mkDTlb#(
noAction;
end
`endif
else if (vm_info.sv39) begin
let vpn = getVpn(r.addr);
let trans_result = tlb.translate(vpn, vm_info.asid);
if (!validVirtualAddress(r.addr)) begin
// page fault
Exception fault = r.write ? excStorePageFault : excLoadPageFault;
pendWait[idx] <= None;
pendResp[idx] <= tuple3(?, Valid (fault), False);
if(verbose) $display("[DTLB] req invalid virtual address: idx %d; ", idx, fshow(r));
end else if (trans_result.hit) begin
// TLB hit
let entry = trans_result.entry;
// check permission
$display("procReq: vm_info: ", fshow(vm_info),
" en : ", fshow(entry),
" r : ", fshow(r)
);
let permCheck = hasVMPermission(vm_info,
entry.pteType,
entry.pteUpperType,
entry.ppn,
entry.level,
r.write ? DataStore : DataLoad,
r.capStore,
r.potentialCapLoad);
$display("Permission check output 2: ", fshow(permCheck));
if (permCheck.allowed) begin
// update TLB replacement info
tlb.updateRepByHit(trans_result.index);
// translate addr
Addr trans_addr = translate(r.addr, entry.ppn, entry.level);
pendWait[idx] <= None;
pendResp[idx] <= tuple3(trans_addr, Invalid, permCheck.allowCap);
if(verbose) begin
$display("[DTLB] req (hit): idx %d; ", idx, fshow(r),
"; ", fshow(trans_result));
end
`ifdef PERF_COUNT
// perf: hit under miss
if(doStats && readVReg(pendWait) != replicate(None)) begin
hitUnderMissCnt.incr(1);
end
`endif
end
else begin
// page fault
Exception fault = permCheck.excCode;
pendWait[idx] <= None;
pendResp[idx] <= tuple3(?, Valid (fault), False);
if(verbose) $display("[DTLB] req no permission: idx %d; ", idx, fshow(r));
end
end
else begin
// TLB miss, req to parent TLB only if there is no existing req
// for the same VPN already waiting for parent TLB resp
function Bool reqSamePage(DTlbReqIdx i);
// we can ignore pendValid here, because not-None pendWait implies
// pendValid is true
let r_i = getTlbReq(pendInst[i]);
return pendWait[i] == WaitParent && getVpn(r.addr) == getVpn(r_i.addr);
endfunction
Vector#(DTlbReqNum, DTlbReqIdx) idxVec = genWith(fromInteger);
if(find(reqSamePage, idxVec) matches tagged Valid .i) begin
// peer entry has already requested, so don't send duplicate req
pendWait[idx] <= WaitPeer (i);
doAssert(pendValid_procReq[i], "peer entry must be valid");
if(verbose) begin
$display("[DTLB] req miss, pend on peer: idx %d, ",
idx, "; ", fshow(r), "; ", fshow(i));
end
end
else begin
// this is the first req for this VPN
pendWait[idx] <= WaitParent;
rqToPQ.enq(DTlbRqToP {
vpn: vpn,
id: idx
});
if(verbose) begin
$display("[DTLB] req miss, send to parent: idx %d, ",
idx, fshow(r));
end
end
// perf: miss
latTimer.start(idx);
end
end
// else if (vm_info.sv39) begin
// let vpn = getVpn(r.addr);
// let trans_result = tlb.translate(vpn, vm_info.asid);
// if (!validVirtualAddress(r.addr)) begin
// // page fault
// Exception fault = r.write ? excStorePageFault : excLoadPageFault;
// pendWait[idx] <= None;
// pendResp[idx] <= tuple3(?, Valid (fault), False);
// if(verbose) $display("[DTLB] req invalid virtual address: idx %d; ", idx, fshow(r));
// end else if (trans_result.hit) begin
// // TLB hit
// let entry = trans_result.entry;
// // check permission
// $display("procReq: vm_info: ", fshow(vm_info),
// " en : ", fshow(entry),
// " r : ", fshow(r)
// );
// let permCheck = hasVMPermission(vm_info,
// entry.pteType,
// entry.pteUpperType,
// entry.ppn,
// entry.level,
// r.write ? DataStore : DataLoad,
// r.capStore,
// r.potentialCapLoad);
// $display("Permission check output 2: ", fshow(permCheck));
// if (permCheck.allowed) begin
// // update TLB replacement info
// tlb.updateRepByHit(trans_result.index);
// // translate addr
// Addr trans_addr = translate(r.addr, entry.ppn, entry.level);
// pendWait[idx] <= None;
// pendResp[idx] <= tuple3(trans_addr, Invalid, permCheck.allowCap);
// if(verbose) begin
// $display("[DTLB] req (hit): idx %d; ", idx, fshow(r),
// "; ", fshow(trans_result));
// end
// `ifdef PERF_COUNT
// // perf: hit under miss
// if(doStats && readVReg(pendWait) != replicate(None)) begin
// hitUnderMissCnt.incr(1);
// end
// `endif
// end
// else begin
// // page fault
// Exception fault = permCheck.excCode;
// pendWait[idx] <= None;
// pendResp[idx] <= tuple3(?, Valid (fault), False);
// if(verbose) $display("[DTLB] req no permission: idx %d; ", idx, fshow(r));
// end
// end
// else begin
// // TLB miss, req to parent TLB only if there is no existing req
// // for the same VPN already waiting for parent TLB resp
// function Bool reqSamePage(DTlbReqIdx i);
// // we can ignore pendValid here, because not-None pendWait implies
// // pendValid is true
// let r_i = getTlbReq(pendInst[i]);
// return pendWait[i] == WaitParent && getVpn(r.addr) == getVpn(r_i.addr);
// endfunction
// Vector#(DTlbReqNum, DTlbReqIdx) idxVec = genWith(fromInteger);
// if(find(reqSamePage, idxVec) matches tagged Valid .i) begin
// // peer entry has already requested, so don't send duplicate req
// pendWait[idx] <= WaitPeer (i);
// doAssert(pendValid_procReq[i], "peer entry must be valid");
// if(verbose) begin
// $display("[DTLB] req miss, pend on peer: idx %d, ",
// idx, "; ", fshow(r), "; ", fshow(i));
// end
// end
// else begin
// // this is the first req for this VPN
// pendWait[idx] <= WaitParent;
// rqToPQ.enq(DTlbRqToP {
// vpn: vpn,
// id: idx
// });
// if(verbose) begin
// $display("[DTLB] req miss, send to parent: idx %d, ",
// idx, fshow(r));
// end
// end
// // perf: miss
// latTimer.start(idx);
// end
// end
else begin
// bare mode
pendWait[idx] <= None;