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Attempt to make toHost setiing behave in src_Testbench

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Made the proc start method non-blocking on mmio platform and wired in a new way
to set the tohost addr using a control and status request, and bumpped
WindCoreInterface accordingly
This commit is contained in:
Alexandre Joannou
2022-09-06 10:42:34 +00:00
parent d068df3bd8
commit a0d471e4f8
4 changed files with 36 additions and 21 deletions
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2
libs/WindCoreInterface

Submodule libs/WindCoreInterface updated: 5af81c8abb...53858449c5

5
src_Core/CPU/MMIOPlatform.bsv
View File

@@ -176,7 +176,7 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
Reg#(DataAlignedAddr) fromHostAddr <- mkReg(0);
// state machine
Reg#(MMIOPlatformState) state <- mkReg(Init);
Reg#(MMIOPlatformState) state <- mkReg (SelectReq);
// current req (valid when state != Init && state != SelectReq
Reg #(MMIOPlatformReq) curReq <- mkRegU;
@@ -1031,10 +1031,9 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
// ================================================================
// INTERFACE
method Action start(Addr toHost, Addr fromHost) if(state == Init);
method Action start(Addr toHost, Addr fromHost);
toHostAddr <= getDataAlignedAddr(toHost);
fromHostAddr <= getDataAlignedAddr(fromHost);
state <= SelectReq;
endmethod
method ActionValue#(Data) to_host;

44
src_Core/Core/CoreW.bsv
View File

@@ -254,19 +254,39 @@ module mkCoreW_reset #(Reset porReset)
TV_Encode_IFC tv_encode <- mkTV_Encode;
`endif
function do_release (restartRunning) = action
Reg #(Bit #(64)) rg_tohost_addr <- mkReg (0);
function do_release (restartRunning, to_host_addr) = action
$display ( "%0d: %m do_release(restartRunning: "
, cur_cycle, fshow (restartRunning), ", to_host_addr: %0h)"
, to_host_addr );
rg_tohost_addr <= to_host_addr;
plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_range.base),
zeroExtend (rangeTop(soc_map.m_plic_addr_range)));
proc.start (restartRunning, soc_map_struct.pc_reset_value, 'h80001000, 0);
proc.start ( restartRunning
, soc_map_struct.pc_reset_value
, to_host_addr
, 0 );
endaction;
// ================================================================
// Start the proc a suitable time after a PoR
Bool start_running = False;
UInt#(8) initial_wait = 100; // heuristic -- better to wait till "all out of reset" received from corew
Reg #(UInt#(8)) rg_corew_start_after_por <- mkReg(initial_wait, reset_by porReset);
rule rl_step_0 (rg_corew_start_after_por != 0);
let n = rg_corew_start_after_por - 1;
rg_corew_start_after_por <= n;
if (n==0) begin
$display ("%0d: %m.rl_step_0, n = 0, do_release", cur_cycle);
do_release(start_running, rg_tohost_addr);
end
endrule
// ================================================================
// Hart-reset from DM
Bool start_running = True;
`ifdef INCLUDE_GDB_CONTROL
Reg #(Bit #(8)) rg_harts_reset_delay <- mkReg (0);
Reg #(Bit #(64)) rg_tohost_addr <- mkReg (0);
Reg #(Bit #(64)) rg_fromhost_addr <- mkReg (0);
for (Integer core = 0; core < valueOf(CoreNum); core = core + 1)
@@ -292,15 +312,6 @@ module mkCoreW_reset #(Reset porReset)
endrule
`endif
// ================================================================
// Start the proc a suitable time after a PoR
UInt#(8) initial_wait = 100; // heuristic -- better to wait till "all out of reset" received from corew
Reg #(UInt#(8)) rg_corew_start_after_por <- mkReg(initial_wait, reset_by porReset);
rule rl_step_0 (rg_corew_start_after_por != 0);
let n = rg_corew_start_after_por - 1;
rg_corew_start_after_por <= n;
if (n==0) do_release(start_running);
endrule
`ifdef INCLUDE_GDB_CONTROL
// ================================================================
@@ -516,7 +527,7 @@ module mkCoreW_reset #(Reset porReset)
endrule
rule rl_debug_module_ack_reset (ndm_reset_delay == 1);
debug_module.ndm_reset_client.response.put (ndm_reset_restart_running);
do_release (ndm_reset_restart_running);
do_release (ndm_reset_restart_running, rg_tohost_addr);
ndm_reset_delay <= 0;
endrule
`else
@@ -554,8 +565,11 @@ module mkCoreW_reset #(Reset porReset)
let f_ctrl_rsps <- mkFIFO1;
rule rl_ctrl_req;
$display ("%0d: %m.rl_ctrl_req", cur_cycle);
case (f_ctrl_reqs.first) matches
tagged ReleaseReq: do_release (False);
tagged ReleaseReq: do_release (True, rg_tohost_addr);
tagged ReleaseAndSetToHostAddrReq .tohost_addr:
do_release (True, tohost_addr);
tagged StatusReq: $display ("StatusReq not supported in Toooba");
endcase
f_ctrl_reqs.deq;

6
src_Testbench/SoC/SoC_Top.bsv
View File

@@ -335,11 +335,13 @@ module mkSoC_Top #(Reset dm_power_on_reset)
// Start CPU execution
// For ISA tests: watch memory writes to <tohost> addr
method Action start (Fabric_Addr tohost_addr, Fabric_Addr fromhost_addr);
method Action start (Fabric_Addr tohost_addr, Fabric_Addr fromhost_addr)
if (rg_state == SOC_IDLE);
Bool watch_tohost = (tohost_addr != 0);
mem0_controller.set_watch_tohost (watch_tohost, tohost_addr);
Bool is_running = True;
corew.controlStatusServer.request.put (ReleaseReq);
corew.controlStatusServer.request.put
(ReleaseAndSetToHostAddrReq (tohost_addr));
$display ("%0d: %m.method start (tohost %0h, fromhost %0h)",
cur_cycle, tohost_addr, fromhost_addr);
endmethod