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Revert "Cover interesting fetch and rename state for DEBUG_WEDGE configs"

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This reverts commit 5e9b478371.
This commit is contained in:
Peter Rugg
2021-01-19 21:39:59 +00:00
parent 6c98dcb3d8
commit a6ab823d1d
6 changed files with 10 additions and 87 deletions
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12
src_Core/CPU/Core.bsv
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@@ -210,10 +210,6 @@ interface Core;
method Tuple2#(CapMem, Bit#(32)) debugLastInst;
(* always_enabled *)
method Tuple4#(Tuple3#(Bit#(32), Bit#(32), Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), void) debugRob;
(* always_enabled *)
method Tuple3#(Bit#(32), Addr, Addr) debugFetch;
(* always_enabled *)
method Bit#(32) debugRename;
`endif
`ifdef PERFORMANCE_MONITORING
@@ -1524,14 +1520,6 @@ module mkCore#(CoreId coreId)(Core);
`ifdef DEBUG_WEDGE
method Tuple2#(CapMem, Bit#(32)) debugLastInst = commitStage.debugLastInst;
method Tuple4#(Tuple3#(Bit#(32), Bit#(32), Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), void) debugRob = rob.debugRob;
method Tuple3#(Bit#(32), Addr, Addr) debugFetch = fetchStage.debugFetch;
method Bit#(32) debugRename;
let epochState = epochManager.getEpochState;
Bit#(8) curEp = zeroExtend(epochState.curEp);
Bit#(8) checkedEp = zeroExtend(epochState.checkedEp);
Bit#(1) pendingMMIOPRq = pack(mmio.hasPendingPRq);
return {15'b0, pendingMMIOPRq, checkedEp, curEp};
endmethod
`endif
`ifdef PERFORMANCE_MONITORING

6
src_Core/CPU/Proc.bsv
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@@ -352,10 +352,8 @@ module mkProc (Proc_IFC);
`endif
`ifdef DEBUG_WEDGE
method Tuple2 #(CapMem, Bit #(32)) hart0_last_inst = core [0].debugLastInst;
method Tuple4 #(Tuple3 #(Bit #(32), Bit #(32), Bit #(32)), Tuple4 #(CapMem, Bit #(32), CapMem, Bit #(32)), Tuple4 #(CapMem, Bit #(32), CapMem, Bit #(32)), void) hart0_debug_rob = core [0].debugRob;
method Tuple3 #(Bit #(32), Addr, Addr) hart0_debug_fetch = core [0].debugFetch;
method Bit #(32) hart0_debug_rename = core [0].debugRename;
method Tuple2#(CapMem, Bit#(32)) hart0_last_inst = core[0].debugLastInst;
method Tuple4#(Tuple3#(Bit#(32), Bit#(32), Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), void) hart0_debug_rob = core[0].debugRob;
`endif
`ifdef PERFORMANCE_MONITORING

8
src_Core/CPU/Proc_IFC.bsv
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@@ -136,13 +136,9 @@ interface Proc_IFC;
`ifdef DEBUG_WEDGE
(* always_enabled *)
method Tuple2 #(CapMem, Bit #(32)) hart0_last_inst;
method Tuple2#(CapMem, Bit#(32)) hart0_last_inst;
(* always_enabled *)
method Tuple4 #(Tuple3 #(Bit #(32), Bit #(32), Bit #(32)), Tuple4 #(CapMem, Bit #(32), CapMem, Bit #(32)), Tuple4 #(CapMem, Bit #(32), CapMem, Bit #(32)), void) hart0_debug_rob;
(* always_enabled *)
method Tuple3 #(Bit #(32), Addr, Addr) hart0_debug_fetch;
(* always_enabled *)
method Bit #(32) hart0_debug_rename;
method Tuple4#(Tuple3#(Bit#(32), Bit#(32), Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), Tuple4#(CapMem, Bit#(32), CapMem, Bit#(32)), void) hart0_debug_rob;
`endif
`ifdef PERFORMANCE_MONITORING

2
src_Core/Core/CoreW.bsv
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@@ -246,8 +246,6 @@ module mkCoreW #(Reset dm_power_on_reset)
`ifdef DEBUG_WEDGE
mkConnection (proc.hart0_last_inst, debug_module.hart0_last_inst);
mkConnection (proc.hart0_debug_rob, debug_module.hart0_debug_rob);
mkConnection (proc.hart0_debug_fetch, debug_module.hart0_debug_fetch);
mkConnection (proc.hart0_debug_rename, debug_module.hart0_debug_rename);
`endif
`endif

34
src_Core/Debug_Module/Debug_Module.bsv
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@@ -139,12 +139,6 @@ interface Debug_Module_IFC;
(* always_enabled *)
method Action hart0_debug_rob (Tuple4 #(Tuple3 #(Bit #(32), Bit #(32), Bit #(32)), Tuple4 #(CapMem, Bit #(32), CapMem, Bit #(32)), Tuple4 #(CapMem, Bit #(32), CapMem, Bit #(32)), void) state);
(* always_enabled *)
method Action hart0_debug_fetch (Tuple3 #(Bit #(32), Addr, Addr) state);
(* always_enabled *)
method Action hart0_debug_rename (Bit #(32) state);
`endif
// ----------------
@@ -192,12 +186,6 @@ module mkDebug_Module (Debug_Module_IFC);
Reg #(Bit #(32)) rg_rob_last0_inst <- mkConfigReg (0);
Reg #(CapMem) rg_rob_last1_pcc <- mkConfigReg (unpack (0));
Reg #(Bit #(32)) rg_rob_last1_inst <- mkConfigReg (0);
Reg #(Bit #(32)) rg_fetch_flags_epoch <- mkConfigReg (0);
Reg #(Addr) rg_fetch_last_itlb <- mkConfigReg (0);
Reg #(Addr) rg_fetch_last_imem <- mkConfigReg (0);
Reg #(Bit #(32)) rg_rename_state <- mkConfigReg (0);
`endif
// ================================================================
@@ -317,27 +305,27 @@ module mkDebug_Module (Debug_Module_IFC);
else if (dm_addr == dm_addr_custom10)
dm_word = rg_fetch_flags_epoch;
dm_word = getAddr (rg_rob_last0_pcc) [31:0];
else if (dm_addr == dm_addr_custom11)
dm_word = rg_fetch_last_itlb [31:0];
dm_word = getAddr (rg_rob_last0_pcc) [63:32];
else if (dm_addr == dm_addr_custom12)
dm_word = rg_fetch_last_itlb [63:32];
dm_word = rg_rob_last0_inst;
else if (dm_addr == dm_addr_custom13)
dm_word = rg_fetch_last_imem [31:0];
dm_word = getAddr (rg_rob_last1_pcc) [31:0];
else if (dm_addr == dm_addr_custom14)
dm_word = rg_fetch_last_imem [63:32];
dm_word = getAddr (rg_rob_last1_pcc) [63:32];
else if (dm_addr == dm_addr_custom15)
dm_word = rg_rename_state;
dm_word = rg_rob_last1_inst;
`endif
else begin
@@ -462,16 +450,6 @@ module mkDebug_Module (Debug_Module_IFC);
rg_rob_last1_pcc <= tpl_3 (tpl_3 (state));
rg_rob_last1_inst <= tpl_4 (tpl_3 (state));
endmethod
method Action hart0_debug_fetch (Tuple3 #(Bit #(32), Addr, Addr) state);
rg_fetch_flags_epoch <= tpl_1 (state);
rg_fetch_last_itlb <= tpl_2 (state);
rg_fetch_last_imem <= tpl_3 (state);
endmethod
method Action hart0_debug_rename (Bit #(32) state);
rg_rename_state <= state;
endmethod
`endif
// ----------------

35
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
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@@ -152,10 +152,6 @@ interface FetchStage;
// debug
method FetchDebugState getFetchState;
`ifdef DEBUG_WEDGE
method Tuple3#(Bit#(32), Addr, Addr) debugFetch;
`endif
// performance
interface Perf#(DecStagePerfType) perf;
endinterface
@@ -564,11 +560,6 @@ module mkFetchStage(FetchStage);
endrule
`endif
`ifdef DEBUG_WEDGE
Reg#(Addr) lastItlbReq <- mkConfigReg(0);
Reg#(Addr) lastImemReq <- mkConfigReg(0);
`endif
// We don't send req to TLB when waiting for redirect or TLB flush. Since
// there is no FIFO between doFetch1 and TLB, when OOO commit stage wait
// TLB idle to change VM CSR / signal flush TLB, there is no wrong path
@@ -606,9 +597,6 @@ module mkFetchStage(FetchStage);
// Send TLB request.
tlb_server.request.put (getAddr(pc));
`ifdef DEBUG_WEDGE
lastItlbReq <= getAddr(pc) & (~ align32b_mask);
`endif
let out = Fetch1ToFetch2 {
pc: pc,
@@ -647,9 +635,6 @@ module mkFetchStage(FetchStage);
MainMem: begin
// Send ICache request
mem_server.request.put(phys_pc);
`ifdef DEBUG_WEDGE
lastImemReq <= phys_pc;
`endif
end
IODevice: begin
// Send MMIO req. Luckily boot rom is also aligned with
@@ -658,25 +643,13 @@ module mkFetchStage(FetchStage);
// boot rom is less than requested.
mmio.bootRomReq(phys_pc, nbSupX2);
access_mmio = True;
`ifdef DEBUG_WEDGE
lastImemReq <= phys_pc;
`endif
end
default: begin
// Access fault
cause = Valid (excInstAccessFault);
`ifdef DEBUG_WEDGE
lastImemReq <= 'hafafafafafafafaf;
`endif
end
endcase
end
`ifdef DEBUG_WEDGE
else begin
// TLB exception
lastImemReq <= 'heeeeeeeeeeeeeeee;
end
`endif
`endif
let out = Fetch2ToFetch3 {
@@ -1287,12 +1260,4 @@ module mkFetchStage(FetchStage);
`endif
endinterface
`ifdef DEBUG_WEDGE
method Tuple3#(Bit#(32), Addr, Addr) debugFetch;
Bit#(7) flags = {pack(out_fifo.deqS[1].canDeq), pack(out_fifo.deqS[0].canDeq), pack(f32d.notEmpty), pack(f22f3.notEmpty), pack(f12f2.notEmpty), pack(waitForFlush), pack(waitForRedirect)};
Bit #(16) epoch = zeroExtend(f_main_epoch);
Bit #(32) flagsEpoch = {8'b0, epoch, 1'b0, flags};
return tuple3(flagsEpoch, lastItlbReq, lastImemReq);
endmethod
`endif
endmodule