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Clean up prints

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This commit is contained in:
Peter Rugg
2022-03-11 10:23:31 +00:00
parent 00c0021479
commit a6b39b58a1
9 changed files with 13 additions and 16 deletions
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2
src_Core/CPU/Core.bsv
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@@ -744,7 +744,7 @@ module mkCore#(CoreId coreId)(Core);
rule drop;
let packets <- commitStage.rvfi.get();
for (Integer i = 0; i < valueOf(SupSize); i = i+1) begin
if (isValid(packets[i])) $display("%t: RVFI ", $time, fshow(packets[i].Valid));
if (isValid(packets[i])) $display("%d: RVFI ", cur_cycle, fshow(packets[i].Valid));
end
endrule
`endif

2
src_Core/CPU/MMIO_AXI4_Adapter.bsv
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@@ -76,7 +76,7 @@ endinterface
module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC);
// Verbosity: 0: quiet; 1: transactions
Integer verbosity = 1;
Integer verbosity = 0;
Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (fromInteger (verbosity));
// ================================================================

5
src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
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@@ -483,8 +483,9 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
mispred: True,
isCompressed: x.isCompressed
});
$display("alu mispredict pc¤: %x, nextPc: %x, %d",
x.controlFlow.pc, x.controlFlow.nextPc, cur_cycle);
if (verbose)
$display("alu mispredict pc: %x, nextPc: %x, %d",
x.controlFlow.pc, x.controlFlow.nextPc, cur_cycle);
`ifdef PERF_COUNT
// performance counter
if(inIfc.doStats) begin

2
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
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@@ -289,7 +289,7 @@ deriving (Eq, FShow, Bits);
module mkCommitStage#(CommitInput inIfc)(CommitStage);
Bool verbose = False;
Integer verbosity = 1; // Bluespec: for lightweight verbosity trace
Integer verbosity = 0; // Bluespec: for lightweight verbosity trace
// Used to inform tandem-verifier about program order.
// 0 is used to indicate we've just come out of reset

2
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
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@@ -540,7 +540,6 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
`ifdef RVFI
memData[pack(x.ldstq_tag)] <= getAddr(data);
$display("%t : memData[%x] <= %x", $time(), pack(x.ldstq_tag), getAddr(data));
`endif
// get shifted data and BE
@@ -856,7 +855,6 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
`ifdef RVFI
LdStQTag idx = tagged Ld tag;
memData[pack(idx)] <= truncate(pack(res.data)); // TODO use fromMem?
$display("%t : memData[%x] <= %x", $time(), pack(idx), res.data);
`endif
end
if(res.wrongPath) begin

2
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
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@@ -732,7 +732,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
doAssert((dInst.iType != Fence) == isValid(dInst.imm),
"Mem (non-Fence) needs imm for virtual addr");
Bit#(16) dum = hash(getAddr(pc));
$display("pc : %x , hash(pc) : %x", pc, dum);
// put in ldstq
if(isLdQ) begin
lsq.enqLd(inst_tag, mem_inst, allow_cap, phy_regs.dst, spec_bits, hash(getAddr(pc)));
@@ -1069,7 +1068,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
doAssert(!isValid(spec_tag), "should not have spec tag");
// put in ldstq
Bit#(16) dum = hash(getAddr(pc));
$display("pc : %x , hash(pc) : %x", pc, dum);
if(isLdQ) begin
lsq.enqLd(inst_tag, mem_inst, phy_regs.dst, spec_bits, hash(getAddr(pc)));
end

9
src_Core/RISCY_OOO/procs/lib/DTlb.bsv
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@@ -287,10 +287,11 @@ module mkDTlb#(
end
else if(pRs.entry matches tagged Valid .en) begin
// check permission
$display("dPRs: vm_info: ", fshow(vm_info),
" en : ", fshow(en),
" r : ", fshow(r)
);
if (verbose)
$display("dPRs: vm_info: ", fshow(vm_info),
" en : ", fshow(en),
" r : ", fshow(r)
);
let permCheck = hasVMPermission(vm_info,
en.pteType,
en.pteUpperType,

3
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
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@@ -674,7 +674,7 @@ module mkSupReorderBuffer#(
Add#(1, a__, aluExeNum), Add#(1, b__, fpuMulDivExeNum)
);
Bool verbose = True;
Bool verbose = False;
// doCommit rule: deq < wrongSpec (overwrite deq in doCommit) < doRenaming rule: enq
Integer valid_deq_port = 0;
@@ -756,7 +756,6 @@ module mkSupReorderBuffer#(
// move deqP & reset valid
deqP[i] <= getNextPtr(deqP[i]);
valid[i][deqP[i]][valid_deq_port] <= False;
$display("deq[%d][%d]", i, deqP[i]);
end
end
// update firstDeqWay: find the first deq port that is not enabled

2
src_Testbench/Top/Mem_Model.bsv
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@@ -81,7 +81,7 @@ typedef Bit#(TSub#(TSub#(TLog#(TSub#(Zeroed_1_end, Zeroed_1_start)), LogZMWidth)
(* synthesize *)
module mkMem_Model (Mem_Model_IFC);
Integer verbosity = 1; // 0 = quiet; 1 = verbose
Integer verbosity = 0; // 0 = quiet; 1 = verbose
Raw_Mem_Addr alloc_size = fromInteger(valueOf(TDiv#(TMul#(Bytes_Per_Mem,8), Bits_per_Raw_Mem_Word))); //(raw mem words)