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Use NonPipelined dividers + update "reset_by" in CoreW

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This commit is contained in:
Alexandre Joannou
2021-08-07 12:07:20 +01:00
parent b32da9034b
commit a954fd5b38
3 changed files with 32 additions and 22 deletions
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22
src_Core/Core/CoreW.bsv
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@@ -224,7 +224,7 @@ module mkCoreResetHelper #(Reset toDbgReset)
`endif
// PLIC (Platform-Level Interrupt Controller)
PLIC_IFC_16_CoreNumX2_7 plic <- mkPLIC_16_CoreNumX2_7;
PLIC_IFC_16_CoreNumX2_7 plic <- mkPLIC_16_CoreNumX2_7 (reset_by all_harts_reset);
`ifdef INCLUDE_GDB_CONTROL
// Debug Module
@@ -279,8 +279,8 @@ module mkCoreResetHelper #(Reset toDbgReset)
// ================================================================
// Direct DM-to-CPU connections for run-control and other misc requests
mkConnection (debug_module.harts_client_run_halt, proc.harts_run_halt_server);
mkConnection (debug_module.harts_get_other_req, proc.harts_put_other_req);
mkConnection (debug_module.harts_client_run_halt, proc.harts_run_halt_server, reset_by toDbgReset);
mkConnection (debug_module.harts_get_other_req, proc.harts_put_other_req, reset_by toDbgReset);
`endif
`ifdef INCLUDE_TANDEM_VERIF
@@ -361,15 +361,15 @@ module mkCoreResetHelper #(Reset toDbgReset)
// BEGIN SECTION: DM, no TV
// Connect DM's GPR interface directly to CPU
mkConnection (debug_module.harts_gpr_mem_client, proc.harts_gpr_mem_server);
mkConnection (debug_module.harts_gpr_mem_client, proc.harts_gpr_mem_server, reset_by toDbgReset);
`ifdef ISA_F_OR_D
// Connect DM's FPR interface directly to CPU
mkConnection (debug_module.harts_fpr_mem_client, proc.harts_fpr_mem_server);
mkConnection (debug_module.harts_fpr_mem_client, proc.harts_fpr_mem_server, reset_by toDbgReset);
`endif
// Connect DM's CSR interface directly to CPU
mkConnection (debug_module.harts_csr_mem_client, proc.harts_csr_mem_server);
mkConnection (debug_module.harts_csr_mem_client, proc.harts_csr_mem_server, reset_by toDbgReset);
// DM's bus master is directly the bus master
let dm_master_local = debug_module.master;
@@ -430,7 +430,7 @@ module mkCoreResetHelper #(Reset toDbgReset)
return res;
endfunction
mkAXI4Bus (route_2x3, master_vector, slave_vector);
mkAXI4Bus (route_2x3, master_vector, slave_vector, reset_by all_harts_reset);
// ================================================================
// Connect external interrupt lines from PLIC to CPU
@@ -469,8 +469,12 @@ module mkCoreResetHelper #(Reset toDbgReset)
endrule
let fromDbgReset <- mkPulseWire (reset_by toDbgReset);
rule rl_debug_module_send_reset;
let _ <- debug_module.ndm_reset_client.request.get;
Reg #(UInt #(8)) ndm_reset_delay <- mkReg (0, reset_by toDbgReset);
Reg #(Bool) ndm_reset_restart_running <- mkReg (True, reset_by toDbgReset);
rule rl_debug_module_send_reset (ndm_reset_delay == 0);
let restartRunning <- debug_module.ndm_reset_client.request.get;
ndm_reset_delay <= 110;
ndm_reset_restart_running <= restartRunning;
fromDbgReset.send;
endrule

24
src_Core/RISCY_OOO/fpgautils/lib/XilinxIntDiv.bsv
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@@ -2,6 +2,9 @@ import FIFOF::*;
import FIFO::*;
import WaitAutoReset::*;
import NonPipelinedMath::*;
import ClientServer::*;
import GetPut::*;
export XilinxIntDiv(..);
export mkXilinxIntDiv;
@@ -70,22 +73,23 @@ module mkIntDivUnsignedSim(IntDivUnsignedImport);
FIFO#(Bit#(64)) divisorQ <- mkFIFO;
FIFOF#(Tuple2#(Bit#(128), IntDivUser)) respQ <- mkSizedFIFOF(2);
FIFO#(IntDivUser) userFF <- mkFIFO;
Server#(Tuple2#(UInt#(128),UInt#(64)),Tuple2#(UInt#(64),UInt#(64)))
nonpipediv <- mkNonPipelinedDividerBlah (4);
rule compute;
dividendQ.deq;
divisorQ.deq;
let {dividend, user} = dividendQ.first;
let divisor = divisorQ.first;
nonpipediv.request.put(tuple2(unpack(zeroExtend(dividend)), unpack(divisor)));
userFF.enq(user);
endrule
// Be careful to avoid divide-by-zero in bluesim's C++, which turns
// res = cond ? exp1 : exp2
// into
// tmp1 = exp1; tmp2 = exp2; res = cond ? tmp1 : tmp2
// so we must give a fake non-zero input even if it looks unused.
UInt#(64) a = unpack(dividend);
UInt#(64) b = divisor == 0 ? 1 : unpack(divisor);
Bit#(64) q = divisor == 0 ? maxBound : pack(a / b);
Bit#(64) r = divisor == 0 ? dividend : pack(a % b);
respQ.enq(tuple2({q, r}, user));
rule getResult;
let {qq, rr} <- nonpipediv.response.get;
let user <- toGet(userFF).get;
respQ.enq(tuple2({pack(qq), pack(rr)}, user));
endrule
method Action enqDividend(Bit#(64) dividend, IntDivUser user);

8
src_Core/RISCY_OOO/procs/lib/Fpu.bsv
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@@ -48,8 +48,9 @@ import FIFO::*;
import FIFOF::*;
import ClientServer::*;
import GetPut::*;
import Divide::*;
import SquareRoot::*;
//import Divide::*;
//import SquareRoot::*;
import NonPipelinedMath :: *;
import FloatingPoint::*;
import XilinxFpu::*;
import HasSpecBits::*;
@@ -95,7 +96,8 @@ module mkDoubleDiv(Server#(Tuple3#(Double, Double, FpuRoundMode), Tuple2#(Double
`ifdef USE_XILINX_FPU
let fpu <- mkXilinxFpDiv;
`else
let int_div <- mkNonPipelinedDivider(3); // [sizhuo] size in RVFpu: 2
//let int_div <- mkDivider(1); // [sizhuo] size in RVFpu: 2
let int_div <- mkNonPipelinedDividerBlah(3);
let fpu <- mkFloatingPointDivider(int_div);
`endif
return fpu;