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Port AXI4 changes from Flute

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This commit is contained in:
Alexandre Joannou
2020-03-22 21:32:19 +00:00
parent 92815e957e
commit b5b2b4fe5c
123 changed files with 570241 additions and 629970 deletions
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84
src_Core/CPU/LLC_AXI4_Adapter.bsv
View File

@@ -29,8 +29,10 @@ import CCTypes :: *;
// ----------------
// From Bluespec Pipes
import AXI4_Types :: *;
import AXI4 :: *;
import SourceSink :: *;
import Fabric_Defs :: *;
import SoC_Map :: *;
// ================================================================
@@ -38,7 +40,9 @@ interface LLC_AXI4_Adapter_IFC;
method Action reset;
// Fabric master interface for memory
interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) mem_master;
interface AXI4_Master_Synth #(Wd_MId, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User) mem_master;
endinterface
// ================================================================
@@ -58,7 +62,7 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
// ================================================================
// Fabric request/response
AXI4_Master_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master_xactor <- mkAXI4_Master_Xactor_2;
let master_xactor <- mkAXI4_Master_Xactor;
// For discarding write-responses
CreditCounter_IFC #(4) ctr_wr_rsps_pending <- mkCreditCounter; // Max 15 writes outstanding
@@ -69,20 +73,20 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
// Send a read-request into the fabric
function Action fa_fabric_send_read_req (Fabric_Addr addr);
action
AXI4_Size size = axsize_8;
let mem_req_rd_addr = AXI4_Rd_Addr {arid: fabric_default_id,
araddr: addr,
arlen: 0, // burst len = arlen+1
arsize: size,
arburst: fabric_default_burst,
arlock: fabric_default_lock,
arcache: fabric_default_arcache,
arprot: fabric_default_prot,
arqos: fabric_default_qos,
arregion: fabric_default_region,
aruser: fabric_default_user};
AXI4_Size size = 8;
let mem_req_rd_addr = AXI4_ARFlit {arid: fabric_default_mid,
araddr: addr,
arlen: 0, // burst len = arlen+1
arsize: size,
arburst: fabric_default_burst,
arlock: fabric_default_lock,
arcache: fabric_default_arcache,
arprot: fabric_default_prot,
arqos: fabric_default_qos,
arregion: fabric_default_region,
aruser: fabric_default_aruser};
master_xactor.i_rd_addr.enq (mem_req_rd_addr);
master_xactor.slave.ar.put(mem_req_rd_addr);
// Debugging
if (cfg_verbosity > 1) begin
@@ -94,35 +98,37 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
// Send a write-request into the fabric
function Action fa_fabric_send_write_req (Fabric_Addr addr, Fabric_Strb strb, Bit #(64) st_val);
action
AXI4_Size size = axsize_8;
let mem_req_wr_addr = AXI4_Wr_Addr {awid: fabric_default_id,
awaddr: addr,
awlen: 0, // burst len = awlen+1
awsize: size,
awburst: fabric_default_burst,
awlock: fabric_default_lock,
awcache: fabric_default_awcache,
awprot: fabric_default_prot,
awqos: fabric_default_qos,
awregion: fabric_default_region,
awuser: fabric_default_user};
AXI4_Size size = 8;
let mem_req_wr_addr = AXI4_AWFlit {awid: fabric_default_mid,
awaddr: addr,
awlen: 0, // burst len = awlen+1
awsize: size,
awburst: fabric_default_burst,
awlock: fabric_default_lock,
awcache: fabric_default_awcache,
awprot: fabric_default_prot,
awqos: fabric_default_qos,
awregion: fabric_default_region,
awuser: 0};
let mem_req_wr_data = AXI4_Wr_Data {wdata: st_val,
wstrb: strb,
wlast: True,
wuser: fabric_default_user};
let mem_req_wr_data = AXI4_WFlit {wdata: st_val,
wstrb: strb,
wlast: True,
wuser: 0};
master_xactor.i_wr_addr.enq (mem_req_wr_addr);
master_xactor.i_wr_data.enq (mem_req_wr_data);
master_xactor.slave.aw.put (mem_req_wr_addr);
master_xactor.slave.w.put (mem_req_wr_data);
// Expect a fabric response
ctr_wr_rsps_pending.incr;
// Debugging
/*
if (cfg_verbosity > 1) begin
$display (" To fabric: ", fshow (mem_req_wr_addr));
$display (" ", fshow (mem_req_wr_data));
end
*/
endaction
endfunction
@@ -159,14 +165,14 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
endrule
rule rl_handle_read_rsps;
let mem_rsp <- pop_o (master_xactor.o_rd_data);
let mem_rsp <- get(master_xactor.slave.r);
if (cfg_verbosity > 1) begin
$display ("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ", cur_cycle, rg_rd_rsp_beat);
$display (" ", fshow (mem_rsp));
end
if (mem_rsp.rresp != axi4_resp_okay) begin
if (mem_rsp.rresp != OKAY) begin
// TODO: need to raise a non-maskable interrupt (NMI) here
$display ("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit", cur_cycle);
$display (" ", fshow (mem_rsp));
@@ -229,7 +235,7 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
// Discard write-responses from the fabric
rule rl_discard_write_rsp;
let wr_resp <- pop_o (master_xactor.o_wr_resp);
let wr_resp <- get(master_xactor.slave.b);
if (cfg_verbosity > 1) begin
$display ("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ", cur_cycle, rg_wr_rsp_beat);
@@ -245,7 +251,7 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
ctr_wr_rsps_pending.decr;
if (wr_resp.bresp != axi4_resp_okay) begin
if (wr_resp.bresp != OKAY) begin
// TODO: need to raise a non-maskable interrupt (NMI) here
$display ("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit", cur_cycle);
$display (" ", fshow (wr_resp));
@@ -268,7 +274,7 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
endmethod
// Fabric interface for memory
interface mem_master = master_xactor.axi_side;
interface mem_master = master_xactor.masterSynth;
endmodule
// ================================================================

47
src_Core/CPU/MMIO_AXI4_Adapter.bsv
View File

@@ -37,7 +37,8 @@ import ProcTypes :: *;
// ----------------
// From Bluespec Pipes
import AXI4_Types :: *;
import AXI4 :: *;
import SourceSink :: *;
import Fabric_Defs :: *;
import SoC_Map :: *;
@@ -49,7 +50,9 @@ interface MMIO_AXI4_Adapter_IFC;
interface Server #(MMIOCRq, MMIODataPRs) core_side;
// Fabric master interface for IO
interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) mmio_master;
interface AXI4_Master_Synth #(Wd_MId_2x3, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User) mmio_master;
endinterface
// ================================================================
@@ -71,7 +74,7 @@ module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC);
// ================================================================
// Fabric request/response
AXI4_Master_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master_xactor <- mkAXI4_Master_Xactor_2;
let master_xactor <- mkAXI4_Master_Xactor;
// For discarding write-responses
CreditCounter_IFC #(4) ctr_wr_rsps_pending <- mkCreditCounter; // Max 15 writes outstanding
@@ -82,8 +85,8 @@ module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC);
// Send a read-request into the fabric
function Action fa_fabric_send_read_req (Fabric_Addr addr);
action
AXI4_Size size = axsize_8;
let mem_req_rd_addr = AXI4_Rd_Addr {arid: fabric_default_id,
AXI4_Size size = 8;
let mem_req_rd_addr = AXI4_ARFlit {arid: fabric_2x3_default_mid,
araddr: addr,
arlen: 0, // burst len = arlen+1
arsize: size,
@@ -93,9 +96,9 @@ module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC);
arprot: fabric_default_prot,
arqos: fabric_default_qos,
arregion: fabric_default_region,
aruser: fabric_default_user};
aruser: fabric_default_aruser};
master_xactor.i_rd_addr.enq (mem_req_rd_addr);
master_xactor.slave.ar.put(mem_req_rd_addr);
// Debugging
if (cfg_verbosity > 0) begin
@@ -107,8 +110,8 @@ module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC);
// Send a write-request into the fabric
function Action fa_fabric_send_write_req (Fabric_Addr addr, Fabric_Strb strb, Bit #(64) st_val);
action
AXI4_Size size = axsize_8;
let mem_req_wr_addr = AXI4_Wr_Addr {awid: fabric_default_id,
AXI4_Size size = 8;
let mem_req_wr_addr = AXI4_AWFlit {awid: fabric_2x3_default_mid,
awaddr: addr,
awlen: 0, // burst len = awlen+1
awsize: size,
@@ -118,12 +121,12 @@ module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC);
awprot: fabric_default_prot,
awqos: fabric_default_qos,
awregion: fabric_default_region,
awuser: fabric_default_user};
awuser: 0};
let mem_req_wr_data = AXI4_Wr_Data {wdata: st_val,
let mem_req_wr_data = AXI4_WFlit {wdata: st_val,
wstrb: strb,
wlast: True,
wuser: fabric_default_user};
wuser: 0};
`ifdef FABRIC64
// Work-around for a misbehavior on Xilinx UART and its
@@ -136,21 +139,23 @@ module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC);
// problem.
if (strb [7:4] == 0 || strb [3:0] == 0) begin
mem_req_wr_addr.awsize = axsize_4;
mem_req_wr_addr.awsize = 4;
end
`endif
master_xactor.i_wr_addr.enq (mem_req_wr_addr);
master_xactor.i_wr_data.enq (mem_req_wr_data);
master_xactor.slave.aw.put (mem_req_wr_addr);
master_xactor.slave.w.put (mem_req_wr_data);
// Expect a fabric response
ctr_wr_rsps_pending.incr;
// Debugging
/*
if (cfg_verbosity > 0) begin
$display (" To fabric: ", fshow (mem_req_wr_addr));
$display (" ", fshow (mem_req_wr_data));
end
*/
endaction
endfunction
@@ -188,19 +193,19 @@ module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC);
// ----------------
rule rl_handle_read_rsps;
let mem_rsp <- pop_o (master_xactor.o_rd_data);
let mem_rsp <- get(master_xactor.slave.r);
if (cfg_verbosity > 0) begin
$display ("%0d: %m.rl_handle_read_rsps ", cur_cycle);
$display (" ", fshow (mem_rsp));
end
if ((cfg_verbosity > 0) && (mem_rsp.rresp != axi4_resp_okay)) begin
if ((cfg_verbosity > 0) && (mem_rsp.rresp != OKAY)) begin
$display ("%0d: %m.rl_handle_read_rsp: fabric response error", cur_cycle);
$display (" ", fshow (mem_rsp));
end
let rsp = MMIODataPRs {valid: (mem_rsp.rresp == axi4_resp_okay),
let rsp = MMIODataPRs {valid: (mem_rsp.rresp == OKAY),
data: mem_rsp.rdata};
f_rsps_to_core.enq (rsp);
@@ -240,7 +245,7 @@ module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC);
// Discard write-responses from the fabric
rule rl_discard_write_rsp;
let wr_resp <- pop_o (master_xactor.o_wr_resp);
let wr_resp <- get(master_xactor.slave.b);
if (cfg_verbosity > 0) begin
$display ("%0d: %m.rl_discard_write_rsp", cur_cycle);
@@ -256,7 +261,7 @@ module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC);
ctr_wr_rsps_pending.decr;
if (wr_resp.bresp != axi4_resp_okay) begin
if (wr_resp.bresp != OKAY) begin
// TODO: need to raise a non-maskable interrupt (NMI) here
$display ("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", cur_cycle);
$display (" ", fshow (wr_resp));
@@ -297,7 +302,7 @@ module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC);
interface Server core_side = toGPServer (f_reqs_from_core, f_rsps_to_core);
// Fabric master interface for IO
interface mmio_master = master_xactor.axi_side;
interface mmio_master = master_xactor.masterSynth;
endmodule
// ================================================================

8
src_Core/CPU/Proc.bsv
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@@ -4,7 +4,7 @@ package Proc;
// Copyright (c) 2018 Massachusetts Institute of Technology
// Portions Copyright (c) 2019-2020 Bluespec, Inc.
//
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
@@ -12,10 +12,10 @@ package Proc;
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
@@ -75,7 +75,7 @@ import LLC_AXI4_Adapter :: *;
import MMIO_AXI4_Adapter :: *;
import SoC_Map :: *;
import AXI4_Types :: *;
import AXI4 :: *;
import Fabric_Defs :: *;
`ifdef INCLUDE_GDB_CONTROL

15
src_Core/CPU/Proc_IFC.bsv
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@@ -14,8 +14,9 @@ import ClientServer :: *;
import ISA_Decls :: *;
import AXI4_Types :: *;
import AXI4 :: *;
import Fabric_Defs :: *;
import SoC_Map :: *;
`ifdef INCLUDE_GDB_CONTROL
import DM_CPU_Req_Rsp :: *;
@@ -48,10 +49,14 @@ interface Proc_IFC;
// SoC fabric connections
// Fabric master interface for memory (from LLC)
interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master0;
interface AXI4_Master_Synth #(Wd_MId, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User) master0;
// Fabric master interface for IO (from MMIOPlatform)
interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master1;
interface AXI4_Master_Synth #(Wd_MId_2x3, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User) master1;
// ----------------
// External interrupts
@@ -76,7 +81,9 @@ interface Proc_IFC;
// ----------------
// Coherent port into LLC (used by Debug Module, DMA engines, ... to read/write memory)
interface AXI4_Slave_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) debug_module_mem_server;
interface AXI4_Slave_Synth #(Wd_SId_2x3, Wd_Addr, Wd_Data,
Wd_AW_User, Wd_W_User, Wd_B_User,
Wd_AR_User, Wd_R_User) debug_module_mem_server;
`ifdef RVFI_DII
interface Toooba_RVFI_DII_Server rvfi_dii_server;