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Revert "Revert biggest scheduling change from potentially problematic commit."

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This one does not actually build with the new BSC compiler.  I forgot to
test the hardware build (with GDB), which is where we have the problem.
This reverts commit b4308e9a6e.
This commit is contained in:
jon
2021-02-19 17:15:53 +00:00
parent 9f0968b1cb
commit b5bce1209a
1 changed files with 7 additions and 7 deletions
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14
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
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@@ -471,7 +471,7 @@ module mkFetchStage(FetchStage);
// Since CSR may be modified, sending wrong path request to TLB may cause problem
// So we stall until the next redirection happens
// The next redirect is either by the trap/system inst or an older one
Reg#(Bool) waitForRedirect <- mkReg(False);
Ehr#(3, Bool) waitForRedirect <- mkEhr(False);
// Stall fetch during the flush triggered by the procesing trap/system inst in commit stage
// We stall until the flush is done
@@ -561,7 +561,7 @@ module mkFetchStage(FetchStage);
// there is no FIFO between doFetch1 and TLB, when OOO commit stage wait
// TLB idle to change VM CSR / signal flush TLB, there is no wrong path
// request afterwards to race with the system code that manage paget table.
rule doFetch1(started && !(waitForRedirect) && !(waitForFlush[0]));
rule doFetch1(started && !(waitForRedirect[0]) && !(waitForFlush[0]));
let pc = pc_reg[pc_fetch1_port];
// Chain of prediction for the next instructions
@@ -1128,7 +1128,7 @@ module mkFetchStage(FetchStage);
dii_pid_reg[0] <= dii_pid;
`endif
started <= True;
waitForRedirect <= False;
waitForRedirect[0] <= False;
waitForFlush[0] <= False;
endmethod
method Action stop();
@@ -1136,7 +1136,7 @@ module mkFetchStage(FetchStage);
endmethod
method Action setWaitRedirect;
waitForRedirect <= True; // Conflict with redirect rule.
waitForRedirect[0] <= True;
endmethod
method Action redirect(
CapMem new_pc
@@ -1152,8 +1152,8 @@ module mkFetchStage(FetchStage);
`endif
f_main_epoch <= (f_main_epoch == fromInteger(valueOf(NumEpochs)-1)) ? 0 : f_main_epoch + 1;
ehr_pending_straddle[1] <= tagged Invalid;
// redirect comes, stop stalling for redirect. Conflict with setWaitRedirect rule.
waitForRedirect <= False;
// redirect comes, stop stalling for redirect
waitForRedirect[1] <= False;
// this redirect may be caused by a trap/system inst in commit stage
// we conservatively set wait for flush TODO make this an input parameter
waitForFlush[2] <= True;
@@ -1216,7 +1216,7 @@ module mkFetchStage(FetchStage);
method FetchDebugState getFetchState;
return FetchDebugState {
pc: getAddr(pc_reg[0]),
waitForRedirect: waitForRedirect,
waitForRedirect: waitForRedirect[0],
waitForFlush: waitForFlush[0],
mainEp: f_main_epoch
};