Resolve some issues to build on mac.

This includes renaming Fifo.bsv to Fifos.bsv to account for a case insensitive file system which confuses this library with FIFO.bsv.
Also this includes an update of the verilator flags that are needed for modern verilator.
Finally, some verilator flag changes for building with LLVM.

builds/Resources/Include_verilator.mk

@@ -34,7 +34,7 @@ SIM_EXE_FILE = exe_HW_sim
 #    --x-initial fast   Optimize uninitialized value
 #    --noassert         Disable all assertions
 
-VERILATOR_FLAGS = --stats                 -LDFLAGS -static --x-assign fast --x-initial fast --noassert
+VERILATOR_FLAGS = --stats --x-assign fast --x-initial fast --noassert
 # VERILATOR_FLAGS = --stats -O3 -CFLAGS -O3 -LDFLAGS -static --x-assign fast --x-initial fast --noassert
 
 # Verilator flags: use the following to include code to generate VCDs

builds/Resources/Verilator_resources/verilator_config.vlt

@@ -3,10 +3,10 @@
 // Flags for verilator
 
 `verilator_config
-lint_off -msg WIDTH
-lint_off -msg CASEINCOMPLETE
-lint_off -msg STMTDLY
-lint_off -msg INITIALDLY
-lint_off -msg UNSIGNED
-lint_off -msg CMPCONST
+lint_off -rule WIDTH
+lint_off -rule CASEINCOMPLETE
+lint_off -rule STMTDLY
+lint_off -rule INITIALDLY
+lint_off -rule UNSIGNED
+lint_off -rule CMPCONST
 `verilog

src_Core/CPU/Core.bsv

@@ -33,7 +33,7 @@ import Assert::*;
 import Cntrs::*;
 import ConfigReg::*;
 import FIFO::*;
-import Fifo::*;
+import Fifos::*;
 import Ehr::*;
 import Connectable::*;
 

src_Core/CPU/CsrFile.bsv

@@ -29,7 +29,7 @@ import DefaultValue::*;
 import ConcatReg::*;
 import ConfigReg::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import Vector::*;
 import FIFO::*;
 import GetPut::*;

src_Core/CPU/MMIOPlatform.bsv

@@ -46,7 +46,7 @@ import GetPut_Aux :: *;
 // ----------------
 // From MIT RISCY-OOO
 
-import Fifo::*;
+import Fifos::*;
 import Types::*;
 import ProcTypes::*;
 import CCTypes::*;

src_Core/RISCY_OOO/coherence/src/CCPipe.bsv

@@ -22,7 +22,7 @@
 // SOFTWARE.
 
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import Vector::*;
 import RWBramCore::*;
 import FShow::*;

src_Core/RISCY_OOO/coherence/src/CrossBar.bsv

@@ -28,7 +28,7 @@ import CacheUtils::*;
 import CCTypes::*;
 import Types::*;
 import FShow::*;
-import Fifo::*;
+import Fifos::*;
 import Ehr::*;
 
 typedef struct {

src_Core/RISCY_OOO/coherence/src/IBank.bsv

@@ -40,7 +40,7 @@ import CCPipe::*;
 import L1Pipe ::*;
 import FShow::*;
 import DefaultValue::*;
-import Fifo::*;
+import Fifos::*;
 import CacheUtils::*;
 import Performance::*;
 import LatencyTimer::*;

src_Core/RISCY_OOO/coherence/src/IPRqMshr.bsv

@@ -31,7 +31,7 @@ import Types::*;
 import CCTypes::*;
 import DefaultValue::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import MshrDeadlockChecker::*;
 
 // MSHR dependency chain invariant:

src_Core/RISCY_OOO/coherence/src/L1Bank.bsv

@@ -41,7 +41,7 @@ import L1Pipe ::*;
 import FShow::*;
 import DefaultValue::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import CacheUtils::*;
 import CrossBar::*;
 import Performance::*;

src_Core/RISCY_OOO/coherence/src/L1PRqMshr.bsv

@@ -30,7 +30,7 @@ import Types::*;
 import CCTypes::*;
 import DefaultValue::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import MshrDeadlockChecker::*;
 
 // MSHR dependency chain invariant:

src_Core/RISCY_OOO/coherence/src/LLBank.bsv

@@ -31,7 +31,7 @@ import CCPipe::*;
 import LLPipe ::*;
 import FShow::*;
 import DefaultValue::*;
-import Fifo::*;
+import Fifos::*;
 import CacheUtils::*;
 import Performance::*;
 import LatencyTimer::*;

src_Core/RISCY_OOO/coherence/src/LLCRqMshr.bsv

@@ -30,7 +30,7 @@ import Types::*;
 import CCTypes::*;
 import DefaultValue::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import MshrDeadlockChecker::*;
 
 // MSHR dependency chain invariant:

src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv

@@ -22,7 +22,7 @@
 // SOFTWARE.
 
 import BRAMCore::*;
-import Fifo::*;
+import Fifos::*;
 
 interface RWBramCore#(type addrT, type dataT);
     method Action wrReq(addrT a, dataT d);

src_Core/RISCY_OOO/coherence/src/RandomReplace.bsv

@@ -22,7 +22,7 @@
 // SOFTWARE.
 
 import Vector::*;
-import Fifo::*;
+import Fifos::*;
 import CCTypes::*;
 import RWBramCore::*;
 

src_Core/RISCY_OOO/coherence/src/SelfInvIBank.bsv

@@ -39,7 +39,7 @@ import CCPipe::*;
 import SelfInvIPipe ::*;
 import FShow::*;
 import DefaultValue::*;
-import Fifo::*;
+import Fifos::*;
 import CacheUtils::*;
 import Performance::*;
 import LatencyTimer::*;

src_Core/RISCY_OOO/coherence/src/SelfInvIPipe.bsv

@@ -26,7 +26,7 @@ import ConfigReg::*;
 import Vector::*;
 import FShow::*;
 import Types::*;
-import Fifo::*;
+import Fifos::*;
 import CCTypes::*;
 import CCPipe::*;
 import RWBramCore::*;

src_Core/RISCY_OOO/coherence/src/SelfInvL1Bank.bsv

@@ -41,7 +41,7 @@ import SelfInvL1Pipe ::*;
 import FShow::*;
 import DefaultValue::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import CacheUtils::*;
 import CrossBar::*;
 import Performance::*;

src_Core/RISCY_OOO/coherence/src/SelfInvL1Pipe.bsv

@@ -25,7 +25,7 @@ import Assert::*;
 import ConfigReg::*;
 import Vector::*;
 import FShow::*;
-import Fifo::*;
+import Fifos::*;
 import Types::*;
 import CCTypes::*;
 import CCPipe::*;

src_Core/RISCY_OOO/coherence/src/SelfInvLLBank.bsv

@@ -30,7 +30,7 @@ import LLCRqMshr::*;
 import CCPipe::*;
 import SelfInvLLPipe ::*;
 import FShow::*;
-import Fifo::*;
+import Fifos::*;
 import CacheUtils::*;
 import Performance::*;
 import LatencyTimer::*;

src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv

@@ -31,7 +31,7 @@ import ClientServer::*;
 import Connectable::*;
 import Decode::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import GetPut::*;
 import MemoryTypes::*;
 import Types::*;

src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv

@@ -27,7 +27,7 @@ import BuildVector::*;
 import GetPut::*;
 import ClientServer::*;
 import Cntrs::*;
-import Fifo::*;
+import Fifos::*;
 import Types::*;
 import ProcTypes::*;
 import MemoryTypes::*;

src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv

@@ -26,7 +26,7 @@
 import Vector::*;
 import GetPut::*;
 import Cntrs::*;
-import Fifo::*;
+import Fifos::*;
 import FIFO::*;
 import Types::*;
 import ProcTypes::*;

src_Core/RISCY_OOO/procs/lib/CacheUtils.bsv

@@ -29,7 +29,7 @@ import GetPut::*;
 import ClientServer::*;
 import Connectable::*;
 import Vector::*;
-import Fifo::*;
+import Fifos::*;
 import Ehr::*;
 import FIFO::*;
 import FIFOF::*;

src_Core/RISCY_OOO/procs/lib/DTlb.bsv

@@ -31,7 +31,7 @@ import TlbTypes::*;
 import Performance::*;
 import FullAssocTlb::*;
 import ConfigReg::*;
-import Fifo::*;
+import Fifos::*;
 import Cntrs::*;
 import SafeCounter::*;
 import CacheUtils::*;

src_Core/RISCY_OOO/procs/lib/ITlb.bsv

@@ -31,7 +31,7 @@ import TlbTypes::*;
 import Performance::*;
 import FullAssocTlb::*;
 import ConfigReg::*;
-import Fifo::*;
+import Fifos::*;
 import Cntrs::*;
 import SafeCounter::*;
 import CacheUtils::*;

src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv

@@ -33,7 +33,7 @@ import CacheUtils::*;
 import Types::*;
 import ProcTypes::*;
 import Performance::*;
-import Fifo::*;
+import Fifos::*;
 import CCTypes::*;
 import L1Pipe::*;
 import L1CRqMshr::*;

src_Core/RISCY_OOO/procs/lib/L2Tlb.bsv

@@ -33,7 +33,7 @@ import Performance::*;
 import FullAssocTlb::*;
 import ConfigReg::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import Cntrs::*;
 import SafeCounter::*;
 import CacheUtils::*;

src_Core/RISCY_OOO/procs/lib/LLCRqMshrSecureModel.bsv

@@ -30,7 +30,7 @@ import Types::*;
 import CCTypes::*;
 import DefaultValue::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import MshrDeadlockChecker::*;
 import LLCRqMshr::*;
 

src_Core/RISCY_OOO/procs/lib/LLCache.bsv

@@ -29,7 +29,7 @@ import Connectable::*;
 import GetPut::*;
 import Assert::*;
 import CacheUtils::*;
-import Fifo::*;
+import Fifos::*;
 import Types::*;
 import ProcTypes::*;
 import CCTypes::*;

src_Core/RISCY_OOO/procs/lib/MMIOCore.bsv

@@ -26,7 +26,7 @@ import ConfigReg::*;
 import ProcTypes::*;
 import MMIOAddrs::*;
 import CacheUtils::*;
-import Fifo::*;
+import Fifos::*;
 import Amo::*;
 import MMIOInst::*;
 

src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv

@@ -23,7 +23,7 @@
 
 import Vector::*;
 import ConfigReg::*;
-import Fifo::*;
+import Fifos::*;
 import Types::*;
 import ProcTypes::*;
 import CCTypes::*;

src_Core/RISCY_OOO/procs/lib/MemLoader.bsv

@@ -29,7 +29,7 @@ import Connectable::*;
 import FShow::*;
 import FIFO::*;
 import Vector::*;
-import Fifo::*;
+import Fifos::*;
 import Types::*;
 import ProcTypes::*;
 import CCTypes::*;

src_Core/RISCY_OOO/procs/lib/MsgFifo.bsv

@@ -21,7 +21,7 @@
 // CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 // SOFTWARE.
 
-import Fifo::*;
+import Fifos::*;
 
 typedef union tagged {
     reqT Req;

src_Core/RISCY_OOO/procs/lib/MulDiv.bsv

@@ -25,7 +25,7 @@
 import BuildVector::*;
 import Types::*;
 import ProcTypes::*;
-import Fifo::*;
+import Fifos::*;
 import FIFO::*;
 import XilinxIntMul::*;
 import XilinxIntDiv::*;

src_Core/RISCY_OOO/procs/lib/Scoreboard.bsv

@@ -24,7 +24,7 @@
 `include "ProcConfig.bsv"
 
 import Vector::*;
-import Fifo::*;
+import Fifos::*;
 import ProcTypes::*;
 import CsrFile::*; // for mkReadOnlyReg
 import Ehr::*;

src_Core/RISCY_OOO/procs/lib/TranslationCache.bsv

@@ -24,7 +24,7 @@
 import Vector::*;
 import Assert::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import Types::*;
 import ProcTypes::*;
 import TlbTypes::*;