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Resolve some issues to build on mac.

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This includes renaming Fifo.bsv to Fifos.bsv to account for a case insensitive file system which confuses this library with FIFO.bsv.
Also this includes an update of the verilator flags that are needed for modern verilator.
Finally, some verilator flag changes for building with LLVM.
This commit is contained in:
Jonathan Woodruff
2020-03-19 19:21:59 +00:00
parent c278e4fe68
commit b830f4bf41
38 changed files with 42 additions and 42 deletions
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2
src_Core/RISCY_OOO/coherence/src/CCPipe.bsv
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@@ -22,7 +22,7 @@
// SOFTWARE.
import Ehr::*;
import Fifo::*;
import Fifos::*;
import Vector::*;
import RWBramCore::*;
import FShow::*;

2
src_Core/RISCY_OOO/coherence/src/CrossBar.bsv
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@@ -28,7 +28,7 @@ import CacheUtils::*;
import CCTypes::*;
import Types::*;
import FShow::*;
import Fifo::*;
import Fifos::*;
import Ehr::*;
typedef struct {

2
src_Core/RISCY_OOO/coherence/src/IBank.bsv
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@@ -40,7 +40,7 @@ import CCPipe::*;
import L1Pipe ::*;
import FShow::*;
import DefaultValue::*;
import Fifo::*;
import Fifos::*;
import CacheUtils::*;
import Performance::*;
import LatencyTimer::*;

2
src_Core/RISCY_OOO/coherence/src/IPRqMshr.bsv
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@@ -31,7 +31,7 @@ import Types::*;
import CCTypes::*;
import DefaultValue::*;
import Ehr::*;
import Fifo::*;
import Fifos::*;
import MshrDeadlockChecker::*;
// MSHR dependency chain invariant:

2
src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
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@@ -41,7 +41,7 @@ import L1Pipe ::*;
import FShow::*;
import DefaultValue::*;
import Ehr::*;
import Fifo::*;
import Fifos::*;
import CacheUtils::*;
import CrossBar::*;
import Performance::*;

2
src_Core/RISCY_OOO/coherence/src/L1PRqMshr.bsv
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@@ -30,7 +30,7 @@ import Types::*;
import CCTypes::*;
import DefaultValue::*;
import Ehr::*;
import Fifo::*;
import Fifos::*;
import MshrDeadlockChecker::*;
// MSHR dependency chain invariant:

2
src_Core/RISCY_OOO/coherence/src/LLBank.bsv
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@@ -31,7 +31,7 @@ import CCPipe::*;
import LLPipe ::*;
import FShow::*;
import DefaultValue::*;
import Fifo::*;
import Fifos::*;
import CacheUtils::*;
import Performance::*;
import LatencyTimer::*;

2
src_Core/RISCY_OOO/coherence/src/LLCRqMshr.bsv
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@@ -30,7 +30,7 @@ import Types::*;
import CCTypes::*;
import DefaultValue::*;
import Ehr::*;
import Fifo::*;
import Fifos::*;
import MshrDeadlockChecker::*;
// MSHR dependency chain invariant:

2
src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv
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@@ -22,7 +22,7 @@
// SOFTWARE.
import BRAMCore::*;
import Fifo::*;
import Fifos::*;
interface RWBramCore#(type addrT, type dataT);
method Action wrReq(addrT a, dataT d);

2
src_Core/RISCY_OOO/coherence/src/RandomReplace.bsv
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@@ -22,7 +22,7 @@
// SOFTWARE.
import Vector::*;
import Fifo::*;
import Fifos::*;
import CCTypes::*;
import RWBramCore::*;

2
src_Core/RISCY_OOO/coherence/src/SelfInvIBank.bsv
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@@ -39,7 +39,7 @@ import CCPipe::*;
import SelfInvIPipe ::*;
import FShow::*;
import DefaultValue::*;
import Fifo::*;
import Fifos::*;
import CacheUtils::*;
import Performance::*;
import LatencyTimer::*;

2
src_Core/RISCY_OOO/coherence/src/SelfInvIPipe.bsv
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@@ -26,7 +26,7 @@ import ConfigReg::*;
import Vector::*;
import FShow::*;
import Types::*;
import Fifo::*;
import Fifos::*;
import CCTypes::*;
import CCPipe::*;
import RWBramCore::*;

2
src_Core/RISCY_OOO/coherence/src/SelfInvL1Bank.bsv
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@@ -41,7 +41,7 @@ import SelfInvL1Pipe ::*;
import FShow::*;
import DefaultValue::*;
import Ehr::*;
import Fifo::*;
import Fifos::*;
import CacheUtils::*;
import CrossBar::*;
import Performance::*;

2
src_Core/RISCY_OOO/coherence/src/SelfInvL1Pipe.bsv
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@@ -25,7 +25,7 @@ import Assert::*;
import ConfigReg::*;
import Vector::*;
import FShow::*;
import Fifo::*;
import Fifos::*;
import Types::*;
import CCTypes::*;
import CCPipe::*;

2
src_Core/RISCY_OOO/coherence/src/SelfInvLLBank.bsv
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@@ -30,7 +30,7 @@ import LLCRqMshr::*;
import CCPipe::*;
import SelfInvLLPipe ::*;
import FShow::*;
import Fifo::*;
import Fifos::*;
import CacheUtils::*;
import Performance::*;
import LatencyTimer::*;