adding current changes

src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv

@@ -320,6 +320,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
     // pipeline fifos
     let dispToRegQ <- mkMemDispToRegFifo;
     let regToExeQ <- mkMemRegToExeFifo;
+    // let trollToExeQ <- mkMemRegToExeFifo;
 
     // wire to recv bypass
     Vector#(TMul#(2, AluExeNum), RWire#(Tuple2#(PhyRIndx, CapPipe))) bypassWire <- replicateM(mkRWire);
@@ -600,6 +601,8 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
         regToExeQ.deq;
         let regToExe = regToExeQ.first;
         let x = regToExe.data;
+        // trollToExeQ.enq(regToExe);
+        // ==============================
         if(verbose) $display("%t : [doExeMem] ", $time, fshow(regToExe));
 
         let shiftBE = DataMemAccess(x.shiftBEData);
@@ -647,10 +650,18 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
     endrule
 
     rule doFinishMem;
+        // trollToExeQ.deq;
+        // let regToExe = trollToExeQ.first;
+        // let lol = regToExe.data;
+        // =============================
         dTlb.deqProcResp;
         let dTlbResp = dTlb.procResp;
-        let x = dTlbResp.inst;
+        let x = dTlbResp.inst;  
         let {paddr, expCause, allowCapPTE} = dTlbResp.resp;
+        // paddr = getAddr(lol.vaddr);
+        // expCause = False;
+        // allowCapPTE = True;
+
         Maybe#(Trap) cause = Invalid;
         if (expCause matches tagged Valid .c) cause = Valid(Exception(c));
 
@@ -754,6 +765,11 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
         $display("KONATAS\t%0d\t%0d\t0\tMem4", cur_cycle, x.u_id);
         $fflush;
 `endif
+        // Try me! 
+        // if (x.mem_func == St) begin
+        //       paddr = 256;
+        // end
+
         // update LSQ
         LSQUpdateAddrResult updRes <- lsq.updateAddr(
             x.ldstq_tag, cause, x.allowCapLoad && allowCapPTE, paddr, isMMIO, x.shiftedBE

src_Core/RISCY_OOO/procs/lib/DTlb.bsv

@@ -144,7 +144,7 @@ typedef union tagged {
 module mkDTlb#(
     function TlbReq getTlbReq(instT inst)
 )(DTlb::DTlb#(instT)) provisos(Bits#(instT, a__));
-    Bool verbose = False;
+    Bool verbose = True;
 
     // TLB array
     DTlbArray tlb <- mkDTlbArray;