Merge branch 'RVFI_DII' into CHERI

builds/Resources/Include_verilator.mk

@@ -34,7 +34,7 @@ SIM_EXE_FILE = exe_HW_sim
 #    --x-initial fast   Optimize uninitialized value
 #    --noassert         Disable all assertions
 
-VERILATOR_FLAGS = --stats                 -LDFLAGS -static --x-assign fast --x-initial fast --noassert
+VERILATOR_FLAGS = --stats --x-assign fast --x-initial fast --noassert
 # VERILATOR_FLAGS = --stats -O3 -CFLAGS -O3 -LDFLAGS -static --x-assign fast --x-initial fast --noassert
 
 # Verilator flags: use the following to include code to generate VCDs

builds/Resources/Verilator_resources/verilator_config.vlt

@@ -3,10 +3,10 @@
 // Flags for verilator
 
 `verilator_config
-lint_off -msg WIDTH
-lint_off -msg CASEINCOMPLETE
-lint_off -msg STMTDLY
-lint_off -msg INITIALDLY
-lint_off -msg UNSIGNED
-lint_off -msg CMPCONST
+lint_off -rule WIDTH
+lint_off -rule CASEINCOMPLETE
+lint_off -rule STMTDLY
+lint_off -rule INITIALDLY
+lint_off -rule UNSIGNED
+lint_off -rule CMPCONST
 `verilog

src_Core/CPU/Core.bsv

@@ -33,7 +33,7 @@ import Assert::*;
 import Cntrs::*;
 import ConfigReg::*;
 import FIFO::*;
-import Fifo::*;
+import Fifos::*;
 import Ehr::*;
 import Connectable::*;
 

src_Core/CPU/CsrFile.bsv

@@ -29,7 +29,7 @@ import DefaultValue::*;
 import ConcatReg::*;
 import ConfigReg::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import Vector::*;
 import FIFO::*;
 import GetPut::*;

src_Core/CPU/MMIOPlatform.bsv

@@ -46,7 +46,7 @@ import GetPut_Aux :: *;
 // ----------------
 // From MIT RISCY-OOO
 
-import Fifo::*;
+import Fifos::*;
 import Types::*;
 import ProcTypes::*;
 import CCTypes::*;

src_Core/RISCY_OOO/coherence/src/CCPipe.bsv

@@ -22,7 +22,7 @@
 // SOFTWARE.
 
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import Vector::*;
 import RWBramCore::*;
 import FShow::*;

src_Core/RISCY_OOO/coherence/src/CrossBar.bsv

@@ -28,7 +28,7 @@ import CacheUtils::*;
 import CCTypes::*;
 import Types::*;
 import FShow::*;
-import Fifo::*;
+import Fifos::*;
 import Ehr::*;
 
 typedef struct {

src_Core/RISCY_OOO/coherence/src/IBank.bsv

@@ -40,7 +40,7 @@ import CCPipe::*;
 import L1Pipe ::*;
 import FShow::*;
 import DefaultValue::*;
-import Fifo::*;
+import Fifos::*;
 import CacheUtils::*;
 import Performance::*;
 import LatencyTimer::*;

src_Core/RISCY_OOO/coherence/src/IPRqMshr.bsv

@@ -31,7 +31,7 @@ import Types::*;
 import CCTypes::*;
 import DefaultValue::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import MshrDeadlockChecker::*;
 
 // MSHR dependency chain invariant:

src_Core/RISCY_OOO/coherence/src/L1Bank.bsv

@@ -41,7 +41,7 @@ import L1Pipe ::*;
 import FShow::*;
 import DefaultValue::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import CacheUtils::*;
 import CrossBar::*;
 import Performance::*;

src_Core/RISCY_OOO/coherence/src/L1PRqMshr.bsv

@@ -30,7 +30,7 @@ import Types::*;
 import CCTypes::*;
 import DefaultValue::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import MshrDeadlockChecker::*;
 
 // MSHR dependency chain invariant:

src_Core/RISCY_OOO/coherence/src/LLBank.bsv

@@ -31,7 +31,7 @@ import CCPipe::*;
 import LLPipe ::*;
 import FShow::*;
 import DefaultValue::*;
-import Fifo::*;
+import Fifos::*;
 import CacheUtils::*;
 import Performance::*;
 import LatencyTimer::*;

src_Core/RISCY_OOO/coherence/src/LLCRqMshr.bsv

@@ -30,7 +30,7 @@ import Types::*;
 import CCTypes::*;
 import DefaultValue::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import MshrDeadlockChecker::*;
 
 // MSHR dependency chain invariant:

src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv

@@ -22,7 +22,7 @@
 // SOFTWARE.
 
 import BRAMCore::*;
-import Fifo::*;
+import Fifos::*;
 
 interface RWBramCore#(type addrT, type dataT);
     method Action wrReq(addrT a, dataT d);

src_Core/RISCY_OOO/coherence/src/RandomReplace.bsv

@@ -22,7 +22,7 @@
 // SOFTWARE.
 
 import Vector::*;
-import Fifo::*;
+import Fifos::*;
 import CCTypes::*;
 import RWBramCore::*;
 

src_Core/RISCY_OOO/coherence/src/SelfInvIBank.bsv

@@ -39,7 +39,7 @@ import CCPipe::*;
 import SelfInvIPipe ::*;
 import FShow::*;
 import DefaultValue::*;
-import Fifo::*;
+import Fifos::*;
 import CacheUtils::*;
 import Performance::*;
 import LatencyTimer::*;

src_Core/RISCY_OOO/coherence/src/SelfInvIPipe.bsv

@@ -26,7 +26,7 @@ import ConfigReg::*;
 import Vector::*;
 import FShow::*;
 import Types::*;
-import Fifo::*;
+import Fifos::*;
 import CCTypes::*;
 import CCPipe::*;
 import RWBramCore::*;

src_Core/RISCY_OOO/coherence/src/SelfInvL1Bank.bsv

@@ -41,7 +41,7 @@ import SelfInvL1Pipe ::*;
 import FShow::*;
 import DefaultValue::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import CacheUtils::*;
 import CrossBar::*;
 import Performance::*;

src_Core/RISCY_OOO/coherence/src/SelfInvL1Pipe.bsv

@@ -25,7 +25,7 @@ import Assert::*;
 import ConfigReg::*;
 import Vector::*;
 import FShow::*;
-import Fifo::*;
+import Fifos::*;
 import Types::*;
 import CCTypes::*;
 import CCPipe::*;

src_Core/RISCY_OOO/coherence/src/SelfInvLLBank.bsv

@@ -30,7 +30,7 @@ import LLCRqMshr::*;
 import CCPipe::*;
 import SelfInvLLPipe ::*;
 import FShow::*;
-import Fifo::*;
+import Fifos::*;
 import CacheUtils::*;
 import Performance::*;
 import LatencyTimer::*;

src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv

@@ -1,7 +1,7 @@
 
 // Copyright (c) 2017 Massachusetts Institute of Technology
 // Portions Copyright (c) 2019-2020 Bluespec, Inc.
-// 
+//
 // Permission is hereby granted, free of charge, to any person
 // obtaining a copy of this software and associated documentation
 // files (the "Software"), to deal in the Software without
@@ -9,10 +9,10 @@
 // modify, merge, publish, distribute, sublicense, and/or sell copies
 // of the Software, and to permit persons to whom the Software is
 // furnished to do so, subject to the following conditions:
-// 
+//
 // The above copyright notice and this permission notice shall be
 // included in all copies or substantial portions of the Software.
-// 
+//
 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
@@ -31,7 +31,7 @@ import ClientServer::*;
 import Connectable::*;
 import Decode::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import FIFOF::*;
 import GetPut::*;
 import MemoryTypes::*;
@@ -487,7 +487,7 @@ module mkFetchStage(FetchStage);
     Fifo#(2, Dii_Ids) dii_instIds <- mkCFFifo;
     Fifo#(2, InstsAndIDs) dii_insts <- mkCFFifo;
     Fifo#(2, Dii_Ids) dii_fetched_ids <- mkCFFifo;
-    
+
     Reg#(Dii_Id) last_trace_id <- mkRegU;
 `endif
 
@@ -654,7 +654,7 @@ module mkFetchStage(FetchStage);
             else
                 $display("Fetch3: Nothing else from Fetch2");
         end
-        
+
         SupCntX2S1 pending_n_items = rg_pending_n_items;
         let out = rg_pending_f32d;
         Maybe #(Tuple3 #(Addr, Bit #(16), Bool)) pending_straddle = ehr_pending_straddle[0];
@@ -933,8 +933,8 @@ module mkFetchStage(FetchStage);
 			// rs1 is invalid, i.e., not link: push
 			ras.ras[i].popPush(False, Valid (push_addr));
 		     end
-                     else if (dInst.iType == Jr) begin // jalr 
-			if (!dst_link && src1_link) begin  
+                     else if (dInst.iType == Jr) begin // jalr
+			if (!dst_link && src1_link) begin
 			   // rd is link while rs1 is not: pop
 			   nextPc = Valid (pop_addr);
 			   ras.ras[i].popPush(True, Invalid);
@@ -1223,7 +1223,7 @@ module mkFetchStage(FetchStage);
         method Bool respValid = perfReqQ.notEmpty;
 `endif
     endinterface
-    
+
 `ifdef RVFI_DII
     interface Client dii;
         interface Get request = toGet(dii_instIds);
@@ -1234,4 +1234,3 @@ module mkFetchStage(FetchStage);
     endmethod
 `endif
 endmodule
- 

src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv

@@ -1,6 +1,6 @@
 
 // Copyright (c) 2017 Massachusetts Institute of Technology
-// 
+//
 // Permission is hereby granted, free of charge, to any person
 // obtaining a copy of this software and associated documentation
 // files (the "Software"), to deal in the Software without
@@ -8,10 +8,10 @@
 // modify, merge, publish, distribute, sublicense, and/or sell copies
 // of the Software, and to permit persons to whom the Software is
 // furnished to do so, subject to the following conditions:
-// 
+//
 // The above copyright notice and this permission notice shall be
 // included in all copies or substantial portions of the Software.
-// 
+//
 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
@@ -27,7 +27,7 @@ import BuildVector::*;
 import GetPut::*;
 import ClientServer::*;
 import Cntrs::*;
-import Fifo::*;
+import Fifos::*;
 import Ehr::*;
 import Types::*;
 import ProcTypes::*;
@@ -175,7 +175,7 @@ interface MemExeInput;
     method Action mmioRespDeq;
 
     // global broadcast methods
-    // set aggressive sb & wake up RS 
+    // set aggressive sb & wake up RS
     method Action setRegReadyAggr_mem(PhyRIndx dst);
     method Action setRegReadyAggr_forward(PhyRIndx dst);
     // write reg file & set conservative sb
@@ -382,7 +382,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
         // executed after address transation
         doAssert(!(x.data.mem_func == St && isValid(x.regs.dst)),
                  "St cannot have dst reg");
-        
+
         // go to next stage
         dispToRegQ.enq(ToSpecFifo {
             data: MemDispatchToRegRead {
@@ -451,7 +451,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
         // get virtual addr & St/Sc/Amo data
         Addr vaddr = x.rVal1 + signExtend(x.imm);
         Data data = x.rVal2;
-        
+
 `ifdef RVFI_DII
         memData[pack(x.ldstq_tag)] <= data;
         $display("%t : memData[%x] <= %x", $time(), pack(x.ldstq_tag), data);
@@ -716,7 +716,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
         end
     endaction
     endfunction
-    
+
     rule doRespLdMem;
         memRespLdQ.deq;
         let {t, d} = memRespLdQ.first;
@@ -851,7 +851,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
         waitLrScAmoMMIOResp <= Invalid;
         // get resp data (need shifting)
         let d <- toGet(respLrScAmoQ).get;
-        Data resp = gatherLoad(lsqDeqLd.paddr, lsqDeqLd.byteEn, lsqDeqLd.unsignedLd, d); 
+        Data resp = gatherLoad(lsqDeqLd.paddr, lsqDeqLd.byteEn, lsqDeqLd.unsignedLd, d);
         // write reg file & set ROB as Executed & wakeup rs
         if(lsqDeqLd.dst matches tagged Valid .dst) begin
             inIfc.writeRegFile(dst.indx, resp);

src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv

@@ -26,7 +26,7 @@
 import Vector::*;
 import GetPut::*;
 import Cntrs::*;
-import Fifo::*;
+import Fifos::*;
 import FIFO::*;
 import Types::*;
 import ProcTypes::*;

src_Core/RISCY_OOO/procs/lib/CacheUtils.bsv

@@ -29,7 +29,7 @@ import GetPut::*;
 import ClientServer::*;
 import Connectable::*;
 import Vector::*;
-import Fifo::*;
+import Fifos::*;
 import Ehr::*;
 import FIFO::*;
 import FIFOF::*;

src_Core/RISCY_OOO/procs/lib/DTlb.bsv

@@ -31,7 +31,7 @@ import TlbTypes::*;
 import Performance::*;
 import FullAssocTlb::*;
 import ConfigReg::*;
-import Fifo::*;
+import Fifos::*;
 import Cntrs::*;
 import SafeCounter::*;
 import CacheUtils::*;

src_Core/RISCY_OOO/procs/lib/ITlb.bsv

@@ -31,7 +31,7 @@ import TlbTypes::*;
 import Performance::*;
 import FullAssocTlb::*;
 import ConfigReg::*;
-import Fifo::*;
+import Fifos::*;
 import Cntrs::*;
 import SafeCounter::*;
 import CacheUtils::*;

src_Core/RISCY_OOO/procs/lib/L1CoCache.bsv

@@ -33,7 +33,7 @@ import CacheUtils::*;
 import Types::*;
 import ProcTypes::*;
 import Performance::*;
-import Fifo::*;
+import Fifos::*;
 import CCTypes::*;
 import L1Pipe::*;
 import L1CRqMshr::*;

src_Core/RISCY_OOO/procs/lib/L2Tlb.bsv

@@ -33,7 +33,7 @@ import Performance::*;
 import FullAssocTlb::*;
 import ConfigReg::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import Cntrs::*;
 import SafeCounter::*;
 import CacheUtils::*;

src_Core/RISCY_OOO/procs/lib/LLCRqMshrSecureModel.bsv

@@ -30,7 +30,7 @@ import Types::*;
 import CCTypes::*;
 import DefaultValue::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import MshrDeadlockChecker::*;
 import LLCRqMshr::*;
 

src_Core/RISCY_OOO/procs/lib/LLCache.bsv

@@ -29,7 +29,7 @@ import Connectable::*;
 import GetPut::*;
 import Assert::*;
 import CacheUtils::*;
-import Fifo::*;
+import Fifos::*;
 import Types::*;
 import ProcTypes::*;
 import CCTypes::*;

src_Core/RISCY_OOO/procs/lib/MMIOCore.bsv

@@ -26,7 +26,7 @@ import ConfigReg::*;
 import ProcTypes::*;
 import MMIOAddrs::*;
 import CacheUtils::*;
-import Fifo::*;
+import Fifos::*;
 import Amo::*;
 import MMIOInst::*;
 

src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv

@@ -23,7 +23,7 @@
 
 import Vector::*;
 import ConfigReg::*;
-import Fifo::*;
+import Fifos::*;
 import Types::*;
 import ProcTypes::*;
 import CCTypes::*;

src_Core/RISCY_OOO/procs/lib/MemLoader.bsv

@@ -29,7 +29,7 @@ import Connectable::*;
 import FShow::*;
 import FIFO::*;
 import Vector::*;
-import Fifo::*;
+import Fifos::*;
 import Types::*;
 import ProcTypes::*;
 import CCTypes::*;

src_Core/RISCY_OOO/procs/lib/MsgFifo.bsv

@@ -21,7 +21,7 @@
 // CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 // SOFTWARE.
 
-import Fifo::*;
+import Fifos::*;
 
 typedef union tagged {
     reqT Req;

src_Core/RISCY_OOO/procs/lib/MulDiv.bsv

@@ -25,7 +25,7 @@
 import BuildVector::*;
 import Types::*;
 import ProcTypes::*;
-import Fifo::*;
+import Fifos::*;
 import FIFO::*;
 import XilinxIntMul::*;
 import XilinxIntDiv::*;

src_Core/RISCY_OOO/procs/lib/Scoreboard.bsv

@@ -24,7 +24,7 @@
 `include "ProcConfig.bsv"
 
 import Vector::*;
-import Fifo::*;
+import Fifos::*;
 import ProcTypes::*;
 import CsrFile::*; // for mkReadOnlyReg
 import Ehr::*;

src_Core/RISCY_OOO/procs/lib/TranslationCache.bsv

@@ -24,7 +24,7 @@
 import Vector::*;
 import Assert::*;
 import Ehr::*;
-import Fifo::*;
+import Fifos::*;
 import Types::*;
 import ProcTypes::*;
 import TlbTypes::*;