Fix tracing of Sc.

Sc is unique in that it writes both memory and a register value.
This implementation works around the fact that the memory store data and
the register write data are sharing the same field in the reorder buffer
by inferring the writeback value of Sc from the byteEnable field.

src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv

@@ -225,6 +225,7 @@ function Maybe#(RVFI_DII_Execution#(DataSz,DataSz)) genRVFI(ToReorderBuffer rot,
                     tagged St .s: begin
                         wmask = rot.traceBundle.memByteEn;
                         wdata = rot.traceBundle.regWriteData;
+                        if (rot.iType == Sc) data = rot.traceBundle.memByteEn[0] ? 0:1;
                     end
                 endcase
             end

src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv

@@ -1353,11 +1353,12 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
             inIfc.rob_setExecuted_doFinishMem_RegData (lsqDeqSt.instTag, resp);
 `endif
         end
+        Bool scFail = (lsqDeqSt.memFunc == Sc && resp != fromInteger(valueof(ScSuccVal)));
         inIfc.rob_setExecuted_deqLSQ(lsqDeqSt.instTag, Invalid, Invalid
 `ifdef RVFI
             , ExtraTraceBundle{
-                regWriteData: fromMemTaggedData(resp),
-                memByteEn: replicate(False)
+                regWriteData: truncate(pack(lsqDeqSt.stData)), // No space for register store value; have to infer from byte enables?
+                memByteEn: scFail ? replicate(False):unpack(truncate(pack(lsqDeqSt.shiftedBE) >> lsqDeqSt.paddr[3:0]))
             }
 `endif
         );