Work in progress: updates to handle stop/step/run from Debug Module
This commit is contained in:
rsnikhil
@@ -84,6 +84,8 @@ import Bypass::*;
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import CsrFile :: *;
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import Cur_Cycle :: *;
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interface CoreReq;
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method Action start(
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Addr startpc,
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@@ -138,6 +140,19 @@ interface Core;
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// Bluespec: external interrupt to enter debug mode
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method Action setDEIP (Bit #(1) v);
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`ifdef INCLUDE_GDB_CONTROL
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method Action halt_to_debug_mode_req;
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(* always_ready *)
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method Bool is_debug_halted;
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method Action resume_from_debug_mode;
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method Data csr_read (Bit #(12) csr_addr);
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method Action csr_write (Bit #(12) csr_addr, Data data);
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`endif
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endinterface
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// fixpoint to instantiate modules
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@@ -158,7 +173,11 @@ module mkCore#(CoreId coreId)(Core);
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outOfReset <= True;
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endrule
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Reg#(Bool) started <- mkReg(False);
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Reg#(Bool) started <- mkReg(False); // only used for deadlock check
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`ifdef INCLUDE_GDB_CONTROL
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Reg#(Bool) rg_debug_halted <- mkReg (False);
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`endif
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// front end
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FetchStage fetchStage <- mkFetchStage;
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@@ -512,6 +531,21 @@ module mkCore#(CoreId coreId)(Core);
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endinterface);
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CommitStage commitStage <- mkCommitStage(commitInput);
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(* mutually_exclusive = "coreFix.aluExe_0.doRegReadAlu, commitStage.rl_enter_debug_mode_flush" *)
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(* mutually_exclusive = "coreFix.aluExe_1.doRegReadAlu, commitStage.rl_enter_debug_mode_flush" *)
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(* mutually_exclusive = "coreFix.aluExe_0.doDispatchAlu, commitStage.rl_enter_debug_mode_flush" *)
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(* mutually_exclusive = "coreFix.aluExe_1.doDispatchAlu, commitStage.rl_enter_debug_mode_flush" *)
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(* mutually_exclusive = "coreFix.fpuMulDivExe_0.doFinishIntMul, commitStage.rl_enter_debug_mode_flush" *)
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(* mutually_exclusive = "coreFix.fpuMulDivExe_0.doFinishIntDiv, commitStage.rl_enter_debug_mode_flush" *)
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(* mutually_exclusive = "coreFix.fpuMulDivExe_0.doFinishFpFma, commitStage.rl_enter_debug_mode_flush" *)
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(* mutually_exclusive = "coreFix.fpuMulDivExe_0.doFinishFpDiv, commitStage.rl_enter_debug_mode_flush" *)
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(* mutually_exclusive = "coreFix.fpuMulDivExe_0.doFinishFpSqrt, commitStage.rl_enter_debug_mode_flush" *)
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(* mutually_exclusive = "coreFix.fpuMulDivExe_0.doFinishFpSqrt, commitStage.rl_enter_debug_mode_flush" *)
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rule rl_bogus_dummy (False);
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// Just to allow the scheduling attributes above
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endrule
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// send rob enq time to reservation stations
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(* fire_when_enabled, no_implicit_conditions *)
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rule sendRobEnqTime;
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@@ -903,6 +937,19 @@ module mkCore#(CoreId coreId)(Core);
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endrule
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`endif
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`ifdef INCLUDE_GDB_CONTROL
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// ================================================================
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// Stopping into debug mode
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rule rl_debug_halt_actions ((! rg_debug_halted) && commitStage.is_debug_halted);
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$display ("%0d: %m.rl_debug_halt_actions", cur_cycle);
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rg_debug_halted <= True;
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endrule
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`endif
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// ================================================================
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interface CoreReq coreReq;
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method Action start(
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Bit#(64) startpc,
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@@ -910,6 +957,9 @@ module mkCore#(CoreId coreId)(Core);
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);
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fetchStage.start(startpc);
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started <= True;
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`ifdef INCLUDE_GDB_CONTROL
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rg_debug_halted <= False;
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`endif
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mmio.setHtifAddrs(toHostAddr, fromHostAddr);
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// start rename debug
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commitStage.startRenameDebug;
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@@ -980,5 +1030,38 @@ module mkCore#(CoreId coreId)(Core);
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// Bluespec: external interrupt to enter debug mode
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method Action setDEIP (v) = csrf.setDEIP (v);
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endmodule
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`ifdef INCLUDE_GDB_CONTROL
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method Action halt_to_debug_mode_req () if (! rg_debug_halted);
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$display ("%0d: %m.halt_to_debug_mode_req", cur_cycle);
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started <= False;
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fetchStage.stop;
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commitStage.halt_to_debug_mode_req;
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endmethod
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method Bool is_debug_halted;
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return rg_debug_halted;
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endmethod
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method Action resume_from_debug_mode if (rg_debug_halted);
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let startpc = csrf.dpc_read;
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fetchStage.resume_from_debug_mode (startpc);
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commitStage.resume_from_debug_mode;
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started <= True;
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rg_debug_halted <= False;
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$display ("%0d: %m.resume_from_debug_mode, dpc = 0x%0h", cur_cycle, startpc);
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endmethod
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// TODO_DEBUG: was part of method cond: commitStage.is_debug_halted &&
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method Data csr_read (Bit #(12) csr_addr) if (rg_debug_halted);
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return csrf.rd (unpack (csr_addr));
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endmethod
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// TODO_DEBUG: was part of method cond: commitStage.is_debug_halted &&
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method Action csr_write (Bit #(12) csr_addr, Data data) if (rg_debug_halted);
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csrf.csrInstWr (unpack (csr_addr), data);
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endmethod
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`endif
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endmodule
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@@ -37,6 +37,8 @@ import GetPut::*;
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import BuildVector::*;
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//import TRNG::*;
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import SoC_Map :: *;
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interface CsrFile;
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// Read
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method Data rd(CSR csr);
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@@ -90,6 +92,24 @@ interface CsrFile;
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// terminate
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method ActionValue#(void) terminate;
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`ifdef INCLUDE_GDB_CONTROL
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// Read dpc
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method Addr dpc_read ();
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// Update dpc
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method Action dpc_write (Addr pc);
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// Check whether to enter Debug Mode based on dcsr.{ebreakm, ebreaks, ebreaku}
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method Bool dcsr_stop_for_break;
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// Check whether to enter Debug Mode based on dcsr.step
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method Bool dcsr_stop_for_step;
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// Update 'cause' in DCSR
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(* always_ready *)
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method Action dcsr_cause_write (Bit #(3) dcsr_cause);
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`endif
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endinterface
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// Fancy Reg functions
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@@ -501,6 +521,30 @@ module mkCsrFile #(Data hartid)(CsrFile);
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StatsCsr stats_module <- mkStatsCsr;
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Reg#(Data) stats_csr = stats_module.reg_ifc;
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`ifdef INCLUDE_GDB_CONTROL
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// DCSR is 32b even in RV64
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Bit #(32) dcsr_reset_value = {4'h4, // [31:28] xdebugver
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12'h0, // [27:16] reserved
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1'h0, // [15] ebreakm
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1'h0, // [14] reserved
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1'h0, // [13] ebreaks
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1'h0, // [12] ebreaku
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1'h0, // [11] stepie
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1'h0, // [10] stopcount
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1'h0, // [9] stoptime
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3'h0, // [8:7] cause // WARNING: 0 is non-standard
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1'h0, // [5] reserved
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1'h1, // [4] mprven
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1'h0, // [3] nmip // non-maskable interrupt pending
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1'h0, // [2] step
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2'h3}; // [1:0] prv (machine mode)
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Reg #(Data) rg_dcsr <- mkReg (zeroExtend (dcsr_reset_value));
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Reg #(Data) rg_dpc <- mkReg (truncate (soc_map_struct.pc_reset_value));
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Reg #(Data) rg_dscratch0 <- mkRegU;
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Reg #(Data) rg_dscratch1 <- mkRegU;
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`endif
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`ifdef SECURITY
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// sanctum machine CSRs
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@@ -607,6 +651,14 @@ module mkCsrFile #(Data hartid)(CsrFile);
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CSRmspec: mspec_csr;
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CSRtrng: trng_csr;
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`endif
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`ifdef INCLUDE_GDB_CONTROL
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CSRdcsr: rg_dcsr; // TODO: take NMI into account (cf. Piccolo/Flute)
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CSRdpc: rg_dpc;
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CSRdscratch0: rg_dscratch0;
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CSRdscratch1: rg_dscratch1;
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`endif
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default: readOnlyReg(64'b0);
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endcase);
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endfunction
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@@ -856,4 +908,40 @@ module mkCsrFile #(Data hartid)(CsrFile);
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method doPerfStats = stats_module.doPerfStats;
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method sendDoStats = stats_module.sendDoStats;
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method recvDoStats = stats_module.recvDoStats;
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// ----------------
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// Bluespec:
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// Methods when Debug Module is present
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`ifdef INCLUDE_GDB_CONTROL
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// Read dpc
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method Addr dpc_read ();
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return rg_dpc;
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endmethod
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// Update dpc
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method Action dpc_write (Addr pc);
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rg_dpc <= pc;
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endmethod
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// Check whether to enter Debug Mode based on dcsr.{ebreakm, ebreaks, ebreaku}
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method Bool dcsr_stop_for_break;
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return case (prv_reg)
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prvM: (rg_dcsr [15] == 1'b1);
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prvS: (rg_dcsr [13] == 1'b1);
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prvU: (rg_dcsr [12] == 1'b1);
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endcase;
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endmethod
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// Check whether to enter Debug Mode based on dcsr.step
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method Bool dcsr_stop_for_step;
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return (rg_dcsr [2] == 1'b1);
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endmethod
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// Update 'cause' in DCSR
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method Action dcsr_cause_write (Bit #(3) dcsr_cause);
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rg_dcsr <= { 32'b0, rg_dcsr [31:9], dcsr_cause, rg_dcsr [5:2], prv_reg };
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endmethod
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`endif
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endmodule
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@@ -92,6 +92,31 @@ import TV_Info :: *;
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// ================================================================
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// Major States of CPU
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typedef enum {CPU_RESET1,
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CPU_RESET2,
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`ifdef INCLUDE_GDB_CONTROL
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CPU_GDB_PAUSING, // On GDB breakpoint, while waiting for fence completion
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`endif
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CPU_DEBUG_MODE, // Stopped (normally for debugger)
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CPU_RUNNING // Normal operation
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} CPU_State
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deriving (Eq, Bits, FShow);
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function Bool fn_is_running (CPU_State cpu_state);
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return ( (cpu_state != CPU_RESET1)
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&& (cpu_state != CPU_RESET2)
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`ifdef INCLUDE_GDB_CONTROL
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&& (cpu_state != CPU_GDB_PAUSING)
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&& (cpu_state != CPU_DEBUG_MODE)
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`endif
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);
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endfunction
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// ================================================================
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(* synthesize *)
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module mkProc (Proc_IFC);
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@@ -108,6 +133,11 @@ module mkProc (Proc_IFC);
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// Verbosity: 0=quiet; 1=instruction trace; 2=more detail
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Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (0);
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// ----------------
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// Major CPU states
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Reg #(CPU_State) rg_state <- mkReg (CPU_RESET1);
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// ----------------
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// Reset requests and responses (TODO: to be implemented)
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@@ -258,6 +288,8 @@ module mkProc (Proc_IFC);
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mmio_axi4_adapter.reset;
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f_reset_rsps.enq (?);
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rg_state <= CPU_RUNNING;
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endrule
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// ----------------
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@@ -287,6 +319,122 @@ module mkProc (Proc_IFC);
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end
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endrule
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// ================================================================
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// ================================================================
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// ================================================================
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// DEBUGGER ACCESS
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`ifdef INCLUDE_GDB_CONTROL
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// ----------------
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// Debug Module Run (resume) control
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// Run command when in debug mode
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rule rl_debug_run ((f_run_halt_reqs.first == True)
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&& (! f_gpr_reqs.notEmpty)
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&& (! f_fpr_reqs.notEmpty)
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&& (! f_csr_reqs.notEmpty)
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&& (rg_state == CPU_DEBUG_MODE));
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// if (cfg_verbosity > 1)
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$display ("%0d: %m.rl_debug_run", cur_cycle);
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f_run_halt_reqs.deq;
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core[0].resume_from_debug_mode;
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rg_state <= CPU_RUNNING;
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// Notify debugger that we've started running
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f_run_halt_rsps.enq (True);
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endrule
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// Run command when already running
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rule rl_debug_run_redundant ((f_run_halt_reqs.first == True)
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&& (! f_gpr_reqs.notEmpty)
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&& (! f_fpr_reqs.notEmpty)
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&& (! f_csr_reqs.notEmpty)
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&& fn_is_running (rg_state));
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// if (cfg_verbosity > 1)
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$display ("%0d: %m.rl_debug_run_redundant", cur_cycle);
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f_run_halt_reqs.deq;
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// Notify debugger that we're running
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f_run_halt_rsps.enq (True);
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endrule
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// ----------------
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// Debug Module Halt control
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rule rl_debug_halt ((f_run_halt_reqs.first == False) && fn_is_running (rg_state));
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// if (cfg_verbosity > 1)
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$display ("%0d: %m.rl_debug_halt", cur_cycle);
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f_run_halt_reqs.deq;
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// Debugger 'halt' request (e.g., GDB '^C' command)
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core[0].halt_to_debug_mode_req;
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rg_state <= CPU_GDB_PAUSING;
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endrule
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rule rl_debug_halted ((rg_state == CPU_GDB_PAUSING) && core [0].is_debug_halted);
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// Notify debugger that we've halted
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f_run_halt_rsps.enq (False);
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// Stop executing rules until ready to restart from debugger
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rg_state <= CPU_DEBUG_MODE;
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// if (cfg_verbosity > 1)
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$display ("%0d: %m.rl_debug_halted", cur_cycle);
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endrule
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rule rl_debug_halt_redundant ((f_run_halt_reqs.first == False) && (! fn_is_running (rg_state)));
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// if (cfg_verbosity > 1)
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$display ("%0d: %m.rl_debug_halt_redundant", cur_cycle);
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f_run_halt_reqs.deq;
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// Notify debugger that we've 'halted'
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f_run_halt_rsps.enq (False);
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$display ("%0d: %m.rl_debug_halt_redundant: CPU already halted; state = ", cur_cycle, fshow (rg_state));
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endrule
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// ----------------
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// Debug Module CSR read/write
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rule rl_debug_read_csr ((rg_state == CPU_DEBUG_MODE) && (! f_csr_reqs.first.write));
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let req <- pop (f_csr_reqs);
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Bit #(12) csr_addr = req.address;
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let data = core [0].csr_read (csr_addr);
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let rsp = DM_CPU_Rsp {ok: True, data: data};
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f_csr_rsps.enq (rsp);
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// if (cur_verbosity > 1)
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$display ("%m.rl_debug_read_csr: csr %0d => 0x%0h",
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csr_addr, data);
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endrule
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rule rl_debug_write_csr ((rg_state == CPU_DEBUG_MODE) && f_csr_reqs.first.write);
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let req <- pop (f_csr_reqs);
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Bit #(12) csr_addr = req.address;
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let data = req.data;
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core [0].csr_write (csr_addr, data);
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let rsp = DM_CPU_Rsp {ok: True, data: ?};
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f_csr_rsps.enq (rsp);
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// if (cur_verbosity > 1)
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$display ("%m.rl_debug_write_csr: csr 0x%0h <= 0x%0h", csr_addr, data);
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endrule
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rule rl_debug_csr_access_busy (rg_state != CPU_DEBUG_MODE);
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let req <- pop (f_csr_reqs);
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let rsp = DM_CPU_Rsp {ok: False, data: ?};
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f_csr_rsps.enq (rsp);
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// if (cur_verbosity > 1)
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$display ("%m.rl_debug_csr_access_busy");
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endrule
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`endif
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// ================================================================
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// ================================================================
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// ================================================================
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@@ -305,7 +453,7 @@ module mkProc (Proc_IFC);
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mmioPlatform.start (tohostAddr, fromhostAddr);
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$display ("Proc.start: startpc = 0x%0h, tohostAddr = 0x%0h, fromhostAddr = %0h",
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$display ("%m.start: startpc = 0x%0h, tohostAddr = 0x%0h, fromhostAddr = %0h",
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startpc, tohostAddr, fromhostAddr);
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endmethod
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