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Tweaks to builds/Resources/Include_..._.mk

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rsnikhil
2020-01-08 19:49:49 -05:00
parent 09340dac13
commit 0f04b9cbe1
3 changed files with 4 additions and 4 deletions
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2
builds/Resources/Include_Common.mk
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@@ -38,7 +38,7 @@ CORE_DIRS = $(REPO)/src_Core/CPU:$(REPO)/src_Core/ISA:$(REPO)/src_Core/Core:$(RE
TESTBENCH_DIRS = $(REPO)/src_Testbench/Top:$(REPO)/src_Testbench/SoC:$(REPO)/src_Testbench/Fabrics/AXI4
BSC_PATH = -p $(ALL_RISCY_DIRS):$(CORE_DIRS):$(TESTBENCH_DIRS):+
BSC_PATH = $(ALL_RISCY_DIRS):$(CORE_DIRS):$(TESTBENCH_DIRS):+
# ----------------
# Top-level file and module

4
builds/Resources/Include_bluesim.mk
View File

@@ -15,7 +15,7 @@ build_dir:
.PHONY: compile
compile: build_dir
@echo "INFO: Re-compiling Core (CPU, Caches)"
bsc -u -elab -sim $(TMP_DIRS) $(BSC_COMPILATION_FLAGS) $(BSC_PATH) $(TOPFILE)
bsc -u -elab -sim $(TMP_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) $(TOPFILE)
@echo "INFO: Re-compiled Core (CPU, Caches)"
# ================================================================
@@ -31,7 +31,7 @@ BSC_C_FLAGS += \
.PHONY: simulator
simulator:
@echo "INFO: linking bsc-compiled objects into Bluesim executable"
bsc -sim -parallel-sim-link 8 +RTS -K32M -RTS \
bsc -sim -parallel-sim-link 8 +RTS -K128M -RTS \
$(TMP_DIRS) \
-e $(TOPMODULE) -o ./$(SIM_EXE_FILE) \
$(BSC_C_FLAGS) \

2
builds/Resources/Include_verilator.mk
View File

@@ -18,7 +18,7 @@ Verilog_RTL:
.PHONY: compile
compile: build_dir Verilog_RTL
@echo "INFO: Verilog RTL generation ..."
bsc -u -elab -verilog $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) $(BSC_PATH) $(TOPFILE)
bsc -u -elab -verilog $(RTL_GEN_DIRS) $(BSC_COMPILATION_FLAGS) -p $(BSC_PATH) $(TOPFILE)
@echo "INFO: Verilog RTL generation finished"
# ================================================================