Implement adaptive stride prefetcher, update prefetcher tests
This commit is contained in:
Karlis Susters
@@ -996,6 +996,218 @@ provisos(
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endmethod
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endmodule
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typedef enum {
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EMPTY = 3'd0, INIT = 3'd1, TRANSIENT = 3'd2, STEADY1 = 3'd3,
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STEADY2 = 3'd4, STEADY3 = 3'd5, STEADY4 = 4'd6, STEADYLAST = 3'd7
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} StrideStateAdaptive deriving (Bits, Eq, FShow);
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typedef struct {
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Bit#(12) lastAddr;
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Bit#(13) stride;
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StrideStateAdaptive state;
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Bit#(4) cLinesPrefetched; //Stores how many cache lines have been prefetched for this instruction
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} StrideEntryAdaptive deriving (Bits, Eq, FShow);
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module mkBRAMStrideAdaptivePCPrefetcher(PCPrefetcher)
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provisos(
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NumAlias#(strideTableSize, 64),
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NumAlias#(cLinesPrefetchMin, 2),
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NumAlias#(cLinesSmallStridePrefetchMax, 3),
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NumAlias#(cLinesBigStridePrefetchMax, 5),
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Alias#(strideTableIndexT, Bit#(TLog#(strideTableSize)))
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);
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RWBramCore#(strideTableIndexT, StrideEntryAdaptive) strideTable <- mkRWBramCoreForwarded;
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FIFOF#(Tuple3#(Addr, Bit#(16), HitOrMiss)) memAccesses <- mkSizedBypassFIFOF(8);
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Reg#(Tuple3#(Addr, Bit#(16), HitOrMiss)) rdRespEntry <- mkReg(?);
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Fifo#(8, Addr) addrToPrefetch <- mkOverflowPipelineFifo;
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FIFO#(Tuple3#(StrideEntryAdaptive, Addr, Bit#(16))) strideEntryForPrefetch <- mkBypassFIFO();
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Reg#(Maybe#(Bit#(4))) cLinesPrefetchedLatest <- mkReg(?);
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PulseWire holdReadReq <- mkPulseWire;
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function StrideStateAdaptive incrementSteady(StrideStateAdaptive state);
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case (state)
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STEADY1: return STEADY2;
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STEADY2: return STEADY3;
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STEADY3: return STEADY4;
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STEADY4: return STEADYLAST;
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STEADYLAST: return STEADYLAST;
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default: return STEADY1;
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endcase
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endfunction
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function Bool stateAtLeastSteady(StrideStateAdaptive state);
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return (state == STEADY1 ||
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state == STEADY2 ||
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state == STEADY3 ||
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state == STEADY4 ||
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state == STEADYLAST);
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endfunction
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function Bit#(4) cLinesAheadToPrefetch(StrideStateAdaptive state, Bit#(13) stride);
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let absStride = abs(stride);
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if (absStride <= 8) begin
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if (state == STEADY4 || state == STEADYLAST) begin
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return fromInteger(valueof(cLinesSmallStridePrefetchMax));
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end
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else begin
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return fromInteger(valueof(cLinesPrefetchMin));
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end
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end
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else begin
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//big strides
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if (state == STEADYLAST) begin
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return fromInteger(valueof(cLinesBigStridePrefetchMax));
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end
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else if (state == STEADY3 || state == STEADY4) begin
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return fromInteger(valueof(cLinesBigStridePrefetchMax))-1;
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end
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else begin
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return fromInteger(valueof(cLinesPrefetchMin));
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end
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end
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endfunction
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rule sendReadReq if (!holdReadReq);
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match {.addr, .pcHash, .hitMiss} = memAccesses.first;
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$display("%t Sending read req for %h!", $time, pcHash);
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strideTable.rdReq(truncate(pcHash));
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rdRespEntry <= memAccesses.first;
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memAccesses.deq;
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endrule
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rule updateStrideEntry;
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//Find slot in vector
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//if miss and slot empty
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//if slot init, put address, stride and move to transit
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//if slot transit or steady, verify stride, and move to steady
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// also put last_prefetched
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//if stride wrong, move to transit
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match {.addr, .pcHash, .hitMiss} = rdRespEntry;
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strideTableIndexT index = truncate(pcHash);
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StrideEntryAdaptive se = strideTable.rdResp;
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strideTable.deqRdResp;
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StrideEntryAdaptive seNext = se;
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Bit#(13) observedStride = {1'b0, addr[11:0]} - {1'b0, se.lastAddr};
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$writeh("%t Stride Prefetcher updateStrideEntry ", $time,
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fshow(hitMiss), " ", addr,
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". Entry ", index, " state is ", fshow(se.state));
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if (se.state == EMPTY) begin
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if (hitMiss == MISS) begin
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seNext.lastAddr = truncate(addr);
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seNext.state = INIT;
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$display(", allocate entry");
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end
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else begin
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$display(", ignore");
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end
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end
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else if (se.state == INIT && observedStride != 0) begin
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seNext.stride = observedStride;
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seNext.state = TRANSIENT;
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seNext.lastAddr = truncate(addr);
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$display(", set stride to %h", seNext.stride);
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end
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else if (se.state == TRANSIENT && observedStride != 0) begin
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if (observedStride == se.stride) begin
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//Here we transition from TRANSIENT to STEADY, so init this field
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seNext.cLinesPrefetched = 0;
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seNext.state = STEADY1;
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$display(", stride %h is confirmed!", seNext.stride);
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end
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else begin
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seNext.state = TRANSIENT;
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seNext.stride = observedStride;
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$display(", old stride is broken! New stride: %h", seNext.stride);
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end
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seNext.lastAddr = truncate(addr);
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end
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else if (stateAtLeastSteady(se.state) && observedStride != 0) begin
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if (observedStride == se.stride) begin
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if (se.lastAddr[11:6] != addr[11:6]) begin
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//This means we have crossed a cache line since last access
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seNext.cLinesPrefetched =
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(se.cLinesPrefetched == 0) ? 0 : se.cLinesPrefetched - 1;
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end
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seNext.state = incrementSteady(se.state);
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$display(", stride %h is sustained, advance STEADY number!", se.stride);
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end
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else if (se.state == STEADY4 || se.state == STEADYLAST) begin
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//Leniency towards some stride changes
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seNext.state = STEADY1;
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seNext.cLinesPrefetched = 0; //We've jumped to some other address, so start fetching again!
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$display(", old stride is broken, but tolerate it! Keep old stride: %h", se.stride);
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end
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else begin
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seNext.state = TRANSIENT;
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seNext.stride = observedStride;
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$display(", old stride is broken! New stride: %h", seNext.stride);
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end
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seNext.lastAddr = truncate(addr);
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end
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else
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$display("");
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strideEntryForPrefetch.enq(tuple3(seNext, addr, pcHash));
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endrule
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rule createPrefetchRequests;
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match {.se, .addr, .pcHash} = strideEntryForPrefetch.first;
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//If this rule is looping, then we'll have a valid cLinesPrefetchedLatest
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Bit#(4) cLinesPrefetched = fromMaybe(se.cLinesPrefetched, cLinesPrefetchedLatest);
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if (stateAtLeastSteady(se.state) &&
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cLinesPrefetched !=
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cLinesAheadToPrefetch(se.state, se.stride)) begin
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//can prefetch
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Bit#(13) strideToUse;
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Bit#(13) cLineSize = fromInteger(valueof(DataSz));
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if (se.stride[12] == 1 && se.stride > -cLineSize) begin
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//stride is negative and jumps less than one cline
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strideToUse = -cLineSize;
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end
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else if (se.stride[12] == 0 && se.stride < cLineSize) begin
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//stride is positive and jumps less than one cline
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strideToUse = cLineSize;
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end
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else begin
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strideToUse = se.stride;
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end
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let reqAddr = addr +
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(signExtend(strideToUse) * zeroExtend(cLinesPrefetched + 1));
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addrToPrefetch.enq(reqAddr);
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// We will still be processing this StrideEntry next cycle,
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// so hold off any potential read requests until we do a writeback
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holdReadReq.send();
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cLinesPrefetchedLatest <= Valid(cLinesPrefetched + 1);
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$display("%t Stride Prefetcher getNextPrefetchAddr requesting %h for entry %h", $time, reqAddr, pcHash[7:0]);
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end
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else begin
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//cant prefetch
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$display("%t Stride Prefetcher no possible prefetch for entry %h", $time, strideTableIndexT'(truncate(pcHash)));
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strideEntryForPrefetch.deq;
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se.cLinesPrefetched = cLinesPrefetched;
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cLinesPrefetchedLatest <= Invalid;
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strideTable.wrReq(truncate(pcHash), se);
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end
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endrule
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method Action reportAccess(Addr addr, Bit#(16) pcHash, HitOrMiss hitMiss);
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memAccesses.enq(tuple3 (addr, pcHash, hitMiss));
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endmethod
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method ActionValue#(Addr) getNextPrefetchAddr;
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addrToPrefetch.deq;
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return addrToPrefetch.first;
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endmethod
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endmodule
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module mkL1IPrefetcher(Prefetcher);
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`ifdef INSTR_PREFETCHER_IN_L1
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`ifdef INSTR_PREFETCHER_NEXT_LINE_ON_ALL
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@@ -1071,6 +1283,8 @@ module mkL1DPrefetcher(PCPrefetcher);
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let m <- mkPCPrefetcherAdapter(mkBlockPrefetcher);
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`elsif DATA_PREFETCHER_STRIDE
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let m <- mkBRAMStridePCPrefetcher;
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`elsif DATA_PREFETCHER_STRIDE_ADAPTIVE
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let m <- mkBRAMStridePCPrefetcher;
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`elsif DATA_PREFETCHER_MARKOV
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let m <- mkPCPrefetcherAdapter(mkBRAMMarkovPrefetcher);
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`endif
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@@ -1087,6 +1301,8 @@ module mkLLDPrefetcherInL1D(PCPrefetcher);
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let m <- mkPCPrefetcherAdapter(mkBlockPrefetcher);
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`elsif DATA_PREFETCHER_STRIDE
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let m <- mkBRAMStridePCPrefetcher;
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`elsif DATA_PREFETCHER_STRIDE_ADAPTIVE
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let m <- mkBRAMStridePCPrefetcher;
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`elsif DATA_PREFETCHER_MARKOV
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let m <- mkPCPrefetcherAdapter(mkBRAMMarkovPrefetcher);
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`endif
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@@ -1103,6 +1319,8 @@ module mkLLDPrefetcher(Prefetcher);
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let m <- mkBlockPrefetcher;
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`elsif DATA_PREFETCHER_STRIDE
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doAssert(False, "Illegal data prefetcher type for LL cache!")
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`elsif DATA_PREFETCHER_STRIDE
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doAssert(False, "Illegal data prefetcher type for LL cache!")
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`elsif DATA_PREFETCHER_MARKOV
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let m <- mkBRAMMarkovPrefetcher;
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`endif
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@@ -58,14 +58,14 @@ module mkTargetTableBRAMTest(Empty);
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t.readReq('h8000); // comes from short table
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endaction
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action
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let x <- t.readRespAndClear(); // comes from short table
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let x <- t.readResp(True); // comes from short table
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doAssert(x == Valid('h800a), "test fail!");
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endaction
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action
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t.readReq('h8000); // comes from long table
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endaction
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action
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let x <- t.readRespAndClear(); // comes from long table
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let x <- t.readResp(True); // comes from long table
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doAssert(x == Valid('h80008000), "test fail!");
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endaction
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action
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@@ -75,7 +75,7 @@ module mkTargetTableBRAMTest(Empty);
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t.readReq('h80000000); // comes from long table
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endaction
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action
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let x <- t.readRespAndClear(); // comes from long table
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let x <- t.readResp(True); // comes from long table
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doAssert(x == Valid('h21230000), "test fail!");
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endaction
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action
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@@ -85,248 +85,20 @@ module mkTargetTableBRAMTest(Empty);
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t.readReq('h7000); // get from short table
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endaction
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action
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let x <- t.readRespAndClear(); // get from short table
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let x <- t.readResp(True); // get from short table
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doAssert(x == Valid('h6fde), "test fail!");
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endaction
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action
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t.readReq('h7000); // get from short table
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endaction
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action
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let x <- t.readRespAndClear(); // get from short table
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let x <- t.readResp(True); // get from short table
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doAssert(x == Invalid, "test fail!"); //entry was removed!
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endaction
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endseq
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);
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endmodule
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module mkMultiWindowPrefetcherTest(Empty);
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//let p <- mkMultipleWindowPrefetcher;
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//TODO pass in value of cachelinesinrange
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let p <- mkMultiWindowPrefetcher;
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mkAutoFSM(
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seq
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// ----- Send misses and stuff to one window -----
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action
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p.reportAccess('h80000040, MISS);
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endaction
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action
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let x <- p.getNextPrefetchAddr;
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doAssert(x == 'h80000080, "test fail!");
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endaction
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action
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let x <- p.getNextPrefetchAddr;
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doAssert(x == 'h800000c0, "test fail!");
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endaction
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action
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p.reportAccess('h800000c0, HIT); //Report hit inside window
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endaction
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action
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let x <- p.getNextPrefetchAddr;
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doAssert(x == 'h80000100, "test fail!");
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endaction
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action
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p.reportAccess('h80004000, HIT); //Report hit outside window
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endaction
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action
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let x <- p.getNextPrefetchAddr; //Previous window still recommended
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doAssert(x == 'h80000140, "test fail!");
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endaction
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action
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p.reportAccess('h80000140, MISS); //Report miss inside window
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endaction
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action
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let x <- p.getNextPrefetchAddr; //Previous window still recommended
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doAssert(x == 'h80000180, "test fail!");
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endaction
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// ----- Allocate other windows -----
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action
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p.reportAccess('h70000000, MISS); //Report miss outside window
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endaction
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action
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let x <- p.getNextPrefetchAddr; //new window recommended
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doAssert(x == 'h70000040, "test fail!");
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endaction
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action
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p.reportAccess('h90000000, MISS); //Report miss outside window
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endaction
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action
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let x <- p.getNextPrefetchAddr; //new window recommended
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doAssert(x == 'h90000040, "test fail!");
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endaction
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action
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p.reportAccess('h60000000, MISS); //Report miss outside window
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endaction
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action
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let x <- p.getNextPrefetchAddr; //new window recommended
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doAssert(x == 'h60000040, "test fail!");
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endaction
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action
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p.reportAccess('h80000180, HIT); //Report hit inside oldest window
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endaction
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action
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let x <- p.getNextPrefetchAddr; //oldest window recommended
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doAssert(x == 'h800001c0, "test fail!");
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endaction
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// ----- Trigger window deletion -----
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action
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p.reportAccess('h50000000, MISS); //Report miss outside window,
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//discard window with 'h70..
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endaction
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action
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let x <- p.getNextPrefetchAddr; //new window recommended
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doAssert(x == 'h50000040, "test fail!");
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endaction
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action
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p.reportAccess('h70000040, HIT); //Report hit inside now deleted window
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endaction
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action
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let x <- p.getNextPrefetchAddr; //most recent window still recommended
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doAssert(x == 'h50000080, "test fail!");
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endaction
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// ----- Reorder some more windows around
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action
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p.reportAccess('h800001c0, MISS); //Report hit inside now deleted window
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endaction
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action
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let x <- p.getNextPrefetchAddr; //most recent window still recommended
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doAssert(x == 'h80000200, "test fail!");
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endaction
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endseq
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);
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endmodule
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module mkMultiWindowTargetPrefetcherTest(Empty);
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//let p <- mkMultipleWindowPrefetcher;
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//TODO pass in value of cachelinesinrange
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let p <- mkMultiWindowTargetPrefetcher;
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mkAutoFSM(
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seq
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// ----- Send misses and stuff to one window -----
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action
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p.reportAccess('h80000040, MISS);
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endaction
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action
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let x <- p.getNextPrefetchAddr;
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doAssert(x == 'h80000080, "test fail!");
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endaction
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action
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let x <- p.getNextPrefetchAddr;
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doAssert(x == 'h800000c0, "test fail!");
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endaction
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action
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p.reportAccess('h800000c0, HIT); //Report hit inside window
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endaction
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action
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let x <- p.getNextPrefetchAddr;
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doAssert(x == 'h80000100, "test fail!");
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endaction
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action
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p.reportAccess('h80004000, HIT); //Report hit outside window
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endaction
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action
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let x <- p.getNextPrefetchAddr; //Previous window still recommended
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doAssert(x == 'h80000140, "test fail!");
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endaction
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action
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p.reportAccess('h80000140, MISS); //Report miss inside window
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endaction
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action
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let x <- p.getNextPrefetchAddr; //Previous window still recommended
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doAssert(x == 'h80000180, "test fail!");
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endaction
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// ----- Allocate other windows -----
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action
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p.reportAccess('h70000000, MISS); //Report miss outside window
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endaction
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action
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let x <- p.getNextPrefetchAddr; //new window recommended
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doAssert(x == 'h70000040, "test fail!");
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endaction
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action
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p.reportAccess('h90000000, MISS); //Report miss outside window
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endaction
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action
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let x <- p.getNextPrefetchAddr; //new window recommended
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doAssert(x == 'h90000040, "test fail!");
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endaction
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action
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p.reportAccess('h60000000, MISS); //Report miss outside window
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endaction
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action
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let x <- p.getNextPrefetchAddr; //new window recommended
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||||
doAssert(x == 'h60000040, "test fail!");
|
||||
endaction
|
||||
action
|
||||
p.reportAccess('h80000180, HIT); //Report hit inside oldest window
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr; //oldest window recommended
|
||||
doAssert(x == 'h800001c0, "test fail!");
|
||||
endaction
|
||||
|
||||
// ----- Trigger window deletion -----
|
||||
action
|
||||
p.reportAccess('h50000000, MISS); //Report miss outside window,
|
||||
//discard window with 'h70..
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr; //new window recommended
|
||||
doAssert(x == 'h50000040, "test fail!");
|
||||
endaction
|
||||
action
|
||||
p.reportAccess('h70000040, HIT); //Report hit inside now deleted window
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr; //most recent window still recommended
|
||||
doAssert(x == 'h50000080, "test fail!");
|
||||
endaction
|
||||
|
||||
// ----- Reorder some more windows around
|
||||
action
|
||||
p.reportAccess('h800001c0, MISS); //Report hit inside now deleted window
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000200, "test fail!");
|
||||
endaction
|
||||
|
||||
// ------ Test saving and prefetching target clines
|
||||
action
|
||||
p.reportAccess('h81000000, MISS); //Report miss somewhere far away
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr; //New window allocated and recommended
|
||||
doAssert(x == 'h81000040, "test fail!");
|
||||
endaction
|
||||
action
|
||||
p.reportAccess('h80000180, MISS); //Report miss back home
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr; //new window recommended
|
||||
doAssert(x == 'h50000000, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h800001c0, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr; //target address recommended
|
||||
doAssert(x == 'h81000000, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000200, "test fail!"); // window addresss recommended
|
||||
endaction
|
||||
endseq
|
||||
);
|
||||
endmodule
|
||||
|
||||
module mkBRAMMultiWindowTargetPrefetcherTest(Empty);
|
||||
let p <- mkBRAMMultiWindowTargetPrefetcher;
|
||||
mkAutoFSM(
|
||||
@@ -451,70 +223,6 @@ module mkBRAMMultiWindowTargetPrefetcherTest(Empty);
|
||||
endseq
|
||||
);
|
||||
endmodule
|
||||
module mkSingleWindowTargetPrefetcherTest(Empty);
|
||||
//let p <- mkMultipleWindowPrefetcher;
|
||||
//TODO pass in value of cachelinesinrange
|
||||
let p <- mkSingleWindowTargetPrefetcher;
|
||||
mkAutoFSM(
|
||||
seq
|
||||
// ----- Send misses and stuff to one window -----
|
||||
action
|
||||
p.reportAccess('h80000040, MISS);
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000080, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h800000c0, "test fail!");
|
||||
endaction
|
||||
action
|
||||
p.reportAccess('h800000c0, HIT); //Report hit inside window
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000100, "test fail!");
|
||||
endaction
|
||||
action
|
||||
p.reportAccess('h80004000, HIT); //Report hit outside window
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr; //Previous window still recommended
|
||||
doAssert(x == 'h80000140, "test fail!");
|
||||
endaction
|
||||
action
|
||||
p.reportAccess('h80000140, MISS); //Report miss inside window
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr; //Previous window still recommended
|
||||
doAssert(x == 'h80000180, "test fail!");
|
||||
endaction
|
||||
action
|
||||
p.reportAccess('h81000000, MISS); //Report miss somewhere far away
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr; //New window allocated and recommended
|
||||
doAssert(x == 'h81000040, "test fail!");
|
||||
endaction
|
||||
action
|
||||
p.reportAccess('h80000100, MISS); //Report miss back home
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000140, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr; //target address recommended
|
||||
doAssert(x == 'h81000000, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000180, "test fail!"); // window addresss recommended
|
||||
endaction
|
||||
endseq
|
||||
);
|
||||
endmodule
|
||||
|
||||
module mkBRAMSingleWindowTargetPrefetcherTest(Empty);
|
||||
let p <- mkBRAMSingleWindowTargetPrefetcher;
|
||||
@@ -589,77 +297,6 @@ module mkBRAMSingleWindowTargetPrefetcherTest(Empty);
|
||||
);
|
||||
endmodule
|
||||
|
||||
module mkStridePCPrefetcherTest(Empty);
|
||||
//let p <- mkMultipleWindowPrefetcher;
|
||||
//TODO pass in value of cachelinesinrange
|
||||
let p <- mkStridePCPrefetcher;
|
||||
mkAutoFSM(
|
||||
seq
|
||||
// ----- Send misses and stuff to one window -----
|
||||
action p.reportAccess('h80000040, 'h0069, MISS); endaction
|
||||
action p.reportAccess('h80000080, 'h0069, HIT); endaction
|
||||
action p.reportAccess('h800000a0, 'h0069, HIT); endaction
|
||||
action p.reportAccess('h800000c0, 'h0069, MISS); endaction
|
||||
action p.reportAccess('h800000e0, 'h0069, MISS); endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000120, "test fail!");
|
||||
endaction
|
||||
action p.reportAccess('h80000100, 'h0069, HIT); endaction
|
||||
action p.reportAccess('h80000120, 'h0069, HIT); endaction
|
||||
action p.reportAccess('h80000140, 'h0069, HIT); endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000180, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h800001c0, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000200, "test fail!");
|
||||
endaction
|
||||
action p.reportAccess('h900001f0, 'h006a, MISS); endaction
|
||||
action p.reportAccess('h900001c0, 'h006a, HIT); endaction
|
||||
action p.reportAccess('h90000190, 'h006a, HIT); endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h90000150, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h90000110, "test fail!");
|
||||
endaction
|
||||
action p.reportAccess('h90000100, 'h006b, MISS); endaction
|
||||
action p.reportAccess('h90000200, 'h006b, MISS); endaction
|
||||
action p.reportAccess('h90000300, 'h006b, MISS); endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h90000400, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h90000500, "test fail!");
|
||||
endaction
|
||||
action p.reportAccess('h90000160, 'h006a, HIT); endaction
|
||||
// -- use older entry
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h900000e0, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h900000a0, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h90000600, "test fail!");
|
||||
endaction
|
||||
endseq
|
||||
);
|
||||
endmodule
|
||||
|
||||
module mkBRAMStridePCPrefetcherTest(Empty);
|
||||
let p <- mkBRAMStridePCPrefetcher;
|
||||
mkAutoFSM(
|
||||
@@ -734,6 +371,109 @@ module mkBRAMStridePCPrefetcherTest(Empty);
|
||||
);
|
||||
endmodule
|
||||
|
||||
module mkBRAMStrideAdaptivePCPrefetcherTest(Empty);
|
||||
let p <- mkBRAMStrideAdaptivePCPrefetcher;
|
||||
mkAutoFSM(
|
||||
seq
|
||||
// ----- Send misses and stuff to one window -----
|
||||
action $display("%t", $time); p.reportAccess('h80000040, 'h0069, MISS); endaction
|
||||
action p.reportAccess('h80000080, 'h0069, HIT); endaction
|
||||
action p.reportAccess('h800000a0, 'h0069, HIT); endaction
|
||||
action p.reportAccess('h800000c0, 'h0069, MISS); endaction
|
||||
action p.reportAccess('h800000e0, 'h0069, MISS); endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000100, "test fail!");
|
||||
endaction
|
||||
action p.reportAccess('h80000100, 'h0069, HIT); endaction
|
||||
action p.reportAccess('h80000120, 'h0069, HIT); endaction
|
||||
action p.reportAccess('h80000140, 'h0069, HIT); endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000140, "test fail!");
|
||||
endaction
|
||||
action endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000180, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h800001c0, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000200, "test fail!");
|
||||
endaction
|
||||
action p.reportAccess('h900001f0, 'h006a, MISS); endaction
|
||||
action p.reportAccess('h900001c0, 'h006a, HIT); endaction
|
||||
action p.reportAccess('h90000190, 'h006a, HIT); endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000240, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000280, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h90000150, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h90000110, "test fail!");
|
||||
endaction
|
||||
action p.reportAccess('h90000100, 'h006b, MISS); endaction
|
||||
action p.reportAccess('h90000200, 'h006b, MISS); endaction
|
||||
action p.reportAccess('h90000300, 'h006b, MISS); endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h90000400, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h90000500, "test fail!");
|
||||
endaction
|
||||
action p.reportAccess('h90000160, 'h006a, HIT); endaction
|
||||
// -- use older entry
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h900000e0, "test fail!");
|
||||
endaction
|
||||
action p.reportAccess('h80000080, 'h0069, MISS); endaction
|
||||
//Tolerate broken stride, request again
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h800000c0, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000100, "test fail!");
|
||||
endaction
|
||||
action p.reportAccess('h80000088, 'h0069, MISS); endaction
|
||||
action p.reportAccess('h80000090, 'h0069, MISS); endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h800000d0, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000110, "test fail!");
|
||||
endaction
|
||||
action p.reportAccess('h80000098, 'h0069, MISS); endaction
|
||||
action p.reportAccess('h800000a0, 'h0069, MISS); endaction
|
||||
action p.reportAccess('h800000a8, 'h0069, MISS); endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000168, "test fail!");
|
||||
endaction
|
||||
action p.reportAccess('h800000b0, 'h0069, MISS); endaction
|
||||
action p.reportAccess('h800000b8, 'h0069, MISS); endaction
|
||||
endseq
|
||||
);
|
||||
endmodule
|
||||
|
||||
module mkBRAMMarkovPrefetcherTest(Empty);
|
||||
//let p <- mkMultipleWindowPrefetcher;
|
||||
//TODO pass in value of cachelinesinrange
|
||||
@@ -781,54 +521,6 @@ module mkBRAMMarkovPrefetcherTest(Empty);
|
||||
endseq
|
||||
);
|
||||
endmodule
|
||||
module mkMarkovPrefetcherTest(Empty);
|
||||
//let p <- mkMultipleWindowPrefetcher;
|
||||
//TODO pass in value of cachelinesinrange
|
||||
let p <- mkMarkovPrefetcher;
|
||||
mkAutoFSM(
|
||||
seq
|
||||
// ----- Send misses and stuff to one window -----
|
||||
action
|
||||
p.reportAccess('h80000000, MISS);
|
||||
endaction
|
||||
action
|
||||
p.reportAccess('h80000700, MISS);
|
||||
endaction
|
||||
action
|
||||
p.reportAccess('h90000000, MISS);
|
||||
endaction
|
||||
action
|
||||
p.reportAccess('ha0000000, MISS);
|
||||
endaction
|
||||
action
|
||||
p.reportAccess('h80000000, HIT); //back to start
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000700, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h90000000, "test fail!");
|
||||
endaction
|
||||
action
|
||||
p.reportAccess('h80000700, HIT);
|
||||
endaction
|
||||
action
|
||||
p.reportAccess('ha0000000, HIT);
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000000, "test fail!");
|
||||
endaction
|
||||
action
|
||||
let x <- p.getNextPrefetchAddr;
|
||||
doAssert(x == 'h80000700, "test fail!");
|
||||
endaction
|
||||
endseq
|
||||
);
|
||||
endmodule
|
||||
|
||||
module mkOverflowPipelineFifoTest(Empty);
|
||||
//let p <- mkMultipleWindowPrefetcher;
|
||||
Fifo#(4, Bit#(8)) p <- mkOverflowPipelineFifo;
|
||||
|
||||
Reference in New Issue
Block a user