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Add a few more core performance counters.

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This commit is contained in:
jon
2020-12-04 18:34:56 +00:00
parent bdc2d494f2
commit d6243be1dd
4 changed files with 73 additions and 16 deletions
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4
src_Core/CPU/Core.bsv
View File

@@ -1103,8 +1103,8 @@ module mkCore#(CoreId coreId)(Core);
// ================================================================
// Performance counters
rule report_commit_events;
hpm_core_events[2] <= commitStage.events;
rule report_events;
hpm_core_events[2] <= unpack(pack(commitStage.events) | pack(coreFix.memExeIfc.events));
endrule
Vector #(1, Bit #(Report_Width)) null_evt = replicate (0);

20
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
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@@ -703,7 +703,11 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
end
end
`endif
`ifdef PERFORMANCE_MONITORING
EventsCore events = unpack(0);
events.evt_TRAP = 1;
events_reg <= events;
`endif
// checks
doAssert(x.rob_inst_state == Executed, "must be executed");
doAssert(x.spec_bits == 0, "cannot have spec bits");
@@ -1088,6 +1092,10 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
SupCnt muldivCnt = 0;
SupCnt auipcCnt = 0;
SupCnt fenceCnt = 0;
SupCnt fpuCnt = 0;
// CHERI-specific counters
SupCnt ldCapCnt = 0;
SupCnt stCapCnt = 0;
`ifdef RVFI
Rvfi_Traces rvfis = replicate(tagged Invalid);
@@ -1208,11 +1216,16 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
Br: brCnt = brCnt + 1;
J : jmpCnt = jmpCnt + 1;
Jr: jrCnt = jrCnt + 1;
Ld: ldCnt = ldCnt + 1;
St: stCnt = stCnt + 1;
Ld: begin
ldCnt = ldCnt + 1;
end
St: begin
stCnt = stCnt + 1;
end
Lr: lrCnt = lrCnt + 1;
Sc: scCnt = scCnt + 1;
Amo: amoCnt = amoCnt + 1;
Fpu: fpuCnt = fpuCnt + 1;
Alu: begin
if (((opcode == opcOpImm) || (opcode == opcOpImm32) || (opcode == opcOp)) && ((funct3 == fnSLL) || (funct3 == fnSR)))
shiftCnt = shiftCnt + 1;
@@ -1286,6 +1299,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
events.evt_AMO = amoCnt;
events.evt_SERIAL_SHIFT = shiftCnt;
events.evt_INT_MUL_DIV_REM = muldivCnt;
events.evt_FP = fpuCnt;
events.evt_FENCE = fenceCnt;
events_reg <= events;
`endif

43
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
View File

@@ -68,6 +68,10 @@ import LatencyTimer::*;
import CHERICap::*;
import CHERICC_Fat::*;
import ISA_Decls_CHERI::*;
`ifdef PERFORMANCE_MONITORING
import PerformanceMonitor::*;
import SpecialWires::*;
`endif
import Cur_Cycle :: *;
@@ -228,6 +232,9 @@ interface MemExePipeline;
interface Server#(void, void) reconcile;
`endif
method Data getPerf(ExeStagePerfType t);
`ifdef PERFORMANCE_MONITORING
method EventsCore events;
`endif
endinterface
module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
@@ -265,6 +272,14 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
Count#(Data) exeFenceRelCnt <- mkCount(0);
`endif
`ifdef PERFORMANCE_MONITORING
Array #(Wire #(EventsCore)) events_wire <- mkDWireOR (3, unpack (0));
Reg #(EventsCore) events_reg <- mkReg(unpack(0));
rule update_events_reg;
events_reg <= events_wire[0];
endrule
`endif
// reservation station
ReservationStationMem rsMem <- mkReservationStationMem;
@@ -352,6 +367,11 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
if(inIfc.doStats) begin
exeStMemLat.incr(zeroExtend(lat));
end
`endif
`ifdef PERFORMANCE_MONITORING
EventsCore events = unpack(0);
if (waitSt.shiftedBE == -1) events.evt_MEM_CAP_STORE = 1;
events_wire[1] <= events;
`endif
// now figure out the data to be written
Vector#(LineSzData, ByteEn) be = replicate(replicate(False));
@@ -372,6 +392,11 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
if(inIfc.doStats) begin
exeStMemLat.incr(zeroExtend(lat));
end
`endif
`ifdef PERFORMANCE_MONITORING
EventsCore events = unpack(0);
if (pack(e.byteEn) == -1) events.evt_MEM_CAP_STORE = 1;
events_wire[1] <= events;
`endif
return tuple2(unpack(pack(e.byteEn)), e.line); // return SB entry
endmethod
@@ -672,6 +697,10 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
};
`else
SBSearchRes sbRes = stb.search(info.paddr, info.shiftedBE);
`endif
`ifdef PERFORMANCE_MONITORING
EventsCore events = unpack(0);
if (pack(info.shiftedBE) == -1) events.evt_MEM_CAP_LOAD = 1;
`endif
// search LSQ
LSQIssueLdResult issRes <- lsq.issueLd(info.tag, info.paddr, info.shiftedBE, sbRes);
@@ -711,11 +740,17 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
default: doAssert(False, "unknow stall reason");
endcase
end
`endif
`ifdef PERFORMANCE_MONITORING
events.evt_LOAD_WAIT = 1;
`endif
end
else begin
doAssert(False, "load is stalled");
end
`ifdef PERFORMANCE_MONITORING
events_wire[0] <= events;
`endif
endaction
endfunction
@@ -1286,6 +1321,11 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
if(inIfc.doStats && lsqDeqSt.memFunc == Sc && resp == fromInteger(valueof(ScSuccVal))) begin
exeScSuccessCnt.incr(1);
end
`endif
`ifdef PERFORMANCE_MONITORING
EventsCore events = unpack(0);
events.evt_SC_SUCCESS = 1;
events_wire[2] <= events;
`endif
endrule
@@ -1518,4 +1558,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
default: 0;
endcase);
endmethod
`ifdef PERFORMANCE_MONITORING
method events = events_reg;
`endif
endmodule

22
src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
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@@ -1049,7 +1049,7 @@ typedef 29 No_Of_Ctrs;
typedef struct {
SupCnt evt_REDIRECT;
SupCnt evt_TLB_EXC; // TODO: Misleading name
SupCnt evt_TRAP;
SupCnt evt_BRANCH;
SupCnt evt_JAL;
SupCnt evt_JALR;
@@ -1064,19 +1064,19 @@ typedef struct {
SupCnt evt_FP;
SupCnt evt_SC_SUCCESS;
SupCnt evt_LOAD_WAIT;
SupCnt evt_STORE_WAIT;
SupCnt evt_STORE_WAIT; // XXX
SupCnt evt_FENCE;
SupCnt evt_F_BUSY_NO_CONSUME;
SupCnt evt_D_BUSY_NO_CONSUME;
SupCnt evt_1_BUSY_NO_CONSUME;
SupCnt evt_2_BUSY_NO_CONSUME;
SupCnt evt_3_BUSY_NO_CONSUME;
SupCnt evt_IMPRECISE_SETBOUND;
SupCnt evt_UNREPRESENTABLE_CAP;
SupCnt evt_F_BUSY_NO_CONSUME; // XXX
SupCnt evt_D_BUSY_NO_CONSUME; // XXX
SupCnt evt_1_BUSY_NO_CONSUME; // XXX
SupCnt evt_2_BUSY_NO_CONSUME; // XXX
SupCnt evt_3_BUSY_NO_CONSUME; // XXX
SupCnt evt_IMPRECISE_SETBOUND; // XXX
SupCnt evt_UNREPRESENTABLE_CAP; // XXX
SupCnt evt_MEM_CAP_LOAD;
SupCnt evt_MEM_CAP_STORE;
SupCnt evt_MEM_CAP_LOAD_TAG_SET;
SupCnt evt_MEM_CAP_STORE_TAG_SET;
SupCnt evt_MEM_CAP_LOAD_TAG_SET; // XXX
SupCnt evt_MEM_CAP_STORE_TAG_SET; // XXX
} EventsCore deriving (Bits, FShow);
typedef TDiv#(SizeOf#(EventsCore),SizeOf#(SupCnt)) EventsCoreElements;
`endif