added test for adding pages

Tests/isa/PageCompileSteps.txt

@@ -0,0 +1,4 @@
+./riscv64-unknown-elf-gcc -nostdlib -nostartfiles   -Wl,-Ttext=0x80000000   Page.S   -o Page.o
+./riscv64-unknown-elf-objcopy --remove-section .bss Page.o Page
+# Copy file
+scp home:/home/akilan/Documents/cheri/riscv/riscv/bin/Page .

Tests/isa/PageTableTest.S

@@ -0,0 +1,98 @@
+.option norvc
+.option norelax
+
+.section .text
+.globl _start
+.globl vm_boot
+
+# --------------------------------------------------
+# Entry point
+# --------------------------------------------------
+_start:
+vm_boot:
+    # Only hart 0
+    csrr    a0, mhartid
+    bnez    a0, hang
+
+    # --------------------------------------------------
+    # Build page table entries
+    # --------------------------------------------------
+
+    # root_pt[0] -> l1_pt
+    la      t0, l1_pt
+    srli    t0, t0, 12
+    slli    t0, t0, 10
+    ori     t0, t0, 0x1          # V
+    la      t1, root_pt
+    sd      t0, 0(t1)
+
+    # l1_pt[0] -> l0_pt
+    la      t0, l0_pt
+    srli    t0, t0, 12
+    slli    t0, t0, 10
+    ori     t0, t0, 0x1          # V
+    la      t1, l1_pt
+    sd      t0, 0(t1)
+
+    # l0_pt[0] -> identity RWX mapping
+    li      t0, (1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<6)
+    la      t1, l0_pt
+    sd      t0, 0(t1)
+
+    # --------------------------------------------------
+    # Enable Sv39 paging
+    # --------------------------------------------------
+
+    la      t0, root_pt
+    srli    t0, t0, 12            # PPN
+    li      t1, (8 << 60)          # MODE = Sv39
+    or      t0, t0, t1
+    csrw    satp, t0
+    sfence.vma zero, zero
+
+    # Signal success
+    la      t0, tohost
+    li      t1, 1
+    sd      t1, 0(t0)
+
+hang:
+    wfi
+    j hang
+
+# --------------------------------------------------
+# Required ISA test symbols
+# --------------------------------------------------
+
+.globl exit
+exit:
+    j exit
+
+# --------------------------------------------------
+# Data section (NO .bss)
+# --------------------------------------------------
+
+.section .data
+.align 3
+
+.globl tohost
+.globl fromhost
+tohost:
+    .dword 0
+fromhost:
+    .dword 0
+
+# --------------------------------------------------
+# Page tables (must be in .data)
+# --------------------------------------------------
+
+.align 12
+root_pt:
+    .zero 4096
+
+.align 12
+l1_pt:
+    .zero 4096
+
+.align 12
+l0_pt:
+    .zero 4096

builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_bluesim/test.txt

@@ -0,0 +1,43 @@
+make -C  ../../Tests/elf_to_hex
+make[1]: Entering directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/Toooba/Tests/elf_to_hex'
+make[1]: 'elf_to_hex' is up to date.
+make[1]: Leaving directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/Toooba/Tests/elf_to_hex'
+../../Tests/elf_to_hex/elf_to_hex  ../../Tests/isa/rv64ui-p-add  Mem.hex
+c_mem_load_elf: ../../Tests/isa/rv64ui-p-add is a 64-bit ELF file
+Section .text.init      : addr         80000000 to addr         80000644; size 0x     644 (= 1604) bytes
+Section .tohost         : addr         80001000 to addr         80001048; size 0x      48 (= 72) bytes
+Section .riscv.attributes: Ignored
+Section .symtab         : Searching for addresses of '_start', 'exit' and 'tohost' symbols
+Writing symbols to:    symbol_table.txt
+    No 'exit' label found
+Section .strtab         : Ignored
+Section .shstrtab       : Ignored
+Min addr:                    80000000 (hex)
+Max addr:                    80001047 (hex)
+Writing mem hex to file 'Mem.hex'
+Subtracting 0x80000000 base from addresses
+./exe_HW_sim  +v1  +tohost
+================================================================
+Bluespec RISC-V standalone system simulation v1.2
+Copyright (c) 2017-2018 Bluespec, Inc. All Rights Reserved.
+================================================================
+2: top.dut_soc_top.rl_reset_start_initial ...
+---- allocated socket for RVFI_DII
+---- RVFI_DII_PORT environment variable not defined, using default port 5001 instead
+---- RVFI_DII socket listening on port 5001
+req addr: 'h0000000000000000, zeroed_0_start: 'h0000000000000000-'h0000000000040000, zeroed_1_start: 'h0000000001f80000-'h0000000001fffff8
+req addr: 'h0000000000000000, zeroed_0_start: 'h0000000000000000-'h0000000000040000, zeroed_1_start: 'h0000000001f80000-'h0000000001fffff8
+74: Mem_Controller.set_addr_map: addr_base 0x80000000 addr_lim 0xc0000000
+  SoC address map:
+  Boot ROM:        0x1000 .. 0x2000
+  Mem0 Controller: 0x80000000 .. 0xc0000000
+  UART0:           0xc0000000 .. 0xc0000080
+74: top.dut_soc_top.rl_reset_complete_initial
+INFO: watch_tohost 1, tohost_addr = 0x80001000, fromhost_addr = 0x0
+75: top.dut_soc_top.method start (tohost 80001000, fromhost 0)
+101: top.dut_soc_top.rl_step_0, n = 0, do_release
+101: top.dut_soc_top do_release(restartRunning: True, to_host_addr: 0)
+101: top.dut_soc_top.proc.method start: startpc 80000000, tohostAddr 0, fromhostAddr 0
+102: top.dut_soc_top.rl_ctrl_req
+102: top.dut_soc_top.proc.method start: startpc 80000000, tohostAddr 80001000, fromhostAddr 0
+102: top.dut_soc_top do_release(restartRunning: True, to_host_addr: 80001000)

builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile

@@ -5,11 +5,12 @@ ARCH ?= RV64ACDFIMSUxCHERI
 
 # ================================================================
 # RISC-V config macros passed into Bluespec 'bsc' compiler
-
+BSC_COMPILATION_FLAGS += -verbose
 # Default ISA test
 
 # TEST ?= rv64ui-p-add
-TEST ?= rv64um-v-mulw
+# TEST ?= rv64um-v-mulw
+TEST ?= Page
 
 #================================================================
 # Parameter settings for MIT RISCY, setup paths etc. for Include_Common

src_Core/CPU/Core.bsv

@@ -244,7 +244,7 @@ deriving (Bits, Eq, FShow);
 
 (* synthesize *)
 module mkCore#(CoreId coreId)(Core);
-    let verbose = False;
+    let verbose = True;
 
    // ================================================================
    Integer verbosity = 0;    // More levels of verbosity control than 'Bool verbose'

src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv

@@ -271,7 +271,7 @@ interface MemExePipeline;
 endinterface
 
 module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
-    Bool verbose = False;
+    Bool verbose = True;
 
     // we change cache request in case of single core, becaues our MSI protocol
     // is not good with single core

src_Core/RISCY_OOO/procs/lib/L2Tlb.bsv

@@ -143,7 +143,7 @@ typedef union tagged {
 
 (* synthesize *)
 module mkL2Tlb(L2Tlb::L2Tlb);
-    Bool verbose = False;
+    Bool verbose = True;
    
     // set associative TLB for 4KB pages
     L2SetAssocTlb tlb4KB <- mkL2SetAssocTlb;
@@ -669,6 +669,7 @@ module mkL2Tlb(L2Tlb::L2Tlb);
                         });
                         pendWait_pageWalk[idx] <= WaitMem;
                     end
+                    $display("Add trans cache entry from L2 tlb");
                     // add to translation cache
                     transCache.addEntry(cRq.vpn, walkLevel, pte.ppn, vm_info.asid);
                 end

src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv

@@ -131,9 +131,9 @@ module mkLLCDmaConnect #( DmaServer#(LLCDmaReqId) llc
                , Wd_AW_User_Periph, Wd_W_User_Periph, Wd_B_User_Periph
                , Wd_AR_User_Periph, Wd_R_User_Periph ))
   provisos (Alias #(dmaRqT, DmaRq #(LLCDmaReqId)));
-    Bool verbose = False;
+    Bool verbose = True;
 
-   Integer verbosity = 0;
+   Integer verbosity = 2;
 
    // Connector to AXI4 fabric
    let slavePortShim <- mkAXI4ShimFF;

src_Core/RISCY_OOO/procs/lib/MemLoader.bsv

@@ -109,7 +109,7 @@ endinterface
 // this module should be clocked under user domain
 (* synthesize *)
 module mkMemLoader#(Clock portalClk, Reset portalRst)(MemLoader);
-    Bool verbose = False;
+    Bool verbose = True;
 
     // MMIO regs
     Reg#(Addr) memStartAddr <- mkReg(0);

src_Core/RISCY_OOO/procs/lib/PhysRFile.bsv

@@ -70,7 +70,7 @@ endinterface
 module mkRFile#(d defaultRegisterValue, Bool lazy)( RFile#(wrNum, rdNum, d) ) provisos (
     NumAlias#(ehrPortNum, TAdd#(wrNum, 1)), Bits#(d, d_Size) // wr [< rd] (only in case lazy = false)
 );
-    let verbose = False;
+    let verbose = True;
 
     // phy reg init val must be 0: because x0 is renamed to phy reg 0,
     // which must be 0 at all time

src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv

@@ -691,7 +691,7 @@ module mkSupReorderBuffer#(
     Add#(1, a__, aluExeNum), Add#(1, b__, fpuMulDivExeNum)
 );
 
-    Bool verbose = False;
+    Bool verbose = True;
 
     // doCommit rule: deq < wrongSpec (overwrite deq in doCommit) < doRenaming rule: enq
     Integer valid_deq_port = 0;

src_Core/RISCY_OOO/procs/lib/ReservationStationEhr.bsv

@@ -85,7 +85,7 @@ module mkReservationStation#(Bool lazySched, Bool lazyEnq, Bool countValid)(
     Add#(1, b__, size)
 );
 
-   Bool verbose = False;
+   Bool verbose = True;
 
     Integer valid_wrongSpec_port = 0;
     Integer valid_dispatch_port = 0; // write valid

test.txt

@@ -0,0 +1,12 @@
+Let me know if this message works well on behalf of all of us.
+
+Hi Jan,
+This is a very small gesture from Jose, Mathews, Yukang and Akilan. We have transferred 200 pounds equally contributed by all of us. As you are moving in and settling into your new place, we hope this can help you and Samantha cover certain expenses like buying furniture or for your very efficient interrail travel pass in the near future.
+
+We will definetely miss the german embassy in Slatefort. Happy new year in advance from all of us!
+
+Regards,
+Jose, Mathews, Yukang and Akilan
+(Your UK representation of transportation
+reform)
+