added test for adding pages

src_Core/CPU/Core.bsv

@@ -244,7 +244,7 @@ deriving (Bits, Eq, FShow);
 
 (* synthesize *)
 module mkCore#(CoreId coreId)(Core);
-    let verbose = False;
+    let verbose = True;
 
    // ================================================================
    Integer verbosity = 0;    // More levels of verbosity control than 'Bool verbose'

src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv

@@ -271,7 +271,7 @@ interface MemExePipeline;
 endinterface
 
 module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
-    Bool verbose = False;
+    Bool verbose = True;
 
     // we change cache request in case of single core, becaues our MSI protocol
     // is not good with single core

src_Core/RISCY_OOO/procs/lib/L2Tlb.bsv

@@ -143,7 +143,7 @@ typedef union tagged {
 
 (* synthesize *)
 module mkL2Tlb(L2Tlb::L2Tlb);
-    Bool verbose = False;
+    Bool verbose = True;
    
     // set associative TLB for 4KB pages
     L2SetAssocTlb tlb4KB <- mkL2SetAssocTlb;
@@ -669,6 +669,7 @@ module mkL2Tlb(L2Tlb::L2Tlb);
                         });
                         pendWait_pageWalk[idx] <= WaitMem;
                     end
+                    $display("Add trans cache entry from L2 tlb");
                     // add to translation cache
                     transCache.addEntry(cRq.vpn, walkLevel, pte.ppn, vm_info.asid);
                 end

src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv

@@ -131,9 +131,9 @@ module mkLLCDmaConnect #( DmaServer#(LLCDmaReqId) llc
                , Wd_AW_User_Periph, Wd_W_User_Periph, Wd_B_User_Periph
                , Wd_AR_User_Periph, Wd_R_User_Periph ))
   provisos (Alias #(dmaRqT, DmaRq #(LLCDmaReqId)));
-    Bool verbose = False;
+    Bool verbose = True;
 
-   Integer verbosity = 0;
+   Integer verbosity = 2;
 
    // Connector to AXI4 fabric
    let slavePortShim <- mkAXI4ShimFF;

src_Core/RISCY_OOO/procs/lib/MemLoader.bsv

@@ -109,7 +109,7 @@ endinterface
 // this module should be clocked under user domain
 (* synthesize *)
 module mkMemLoader#(Clock portalClk, Reset portalRst)(MemLoader);
-    Bool verbose = False;
+    Bool verbose = True;
 
     // MMIO regs
     Reg#(Addr) memStartAddr <- mkReg(0);

src_Core/RISCY_OOO/procs/lib/PhysRFile.bsv

@@ -70,7 +70,7 @@ endinterface
 module mkRFile#(d defaultRegisterValue, Bool lazy)( RFile#(wrNum, rdNum, d) ) provisos (
     NumAlias#(ehrPortNum, TAdd#(wrNum, 1)), Bits#(d, d_Size) // wr [< rd] (only in case lazy = false)
 );
-    let verbose = False;
+    let verbose = True;
 
     // phy reg init val must be 0: because x0 is renamed to phy reg 0,
     // which must be 0 at all time

src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv

@@ -691,7 +691,7 @@ module mkSupReorderBuffer#(
     Add#(1, a__, aluExeNum), Add#(1, b__, fpuMulDivExeNum)
 );
 
-    Bool verbose = False;
+    Bool verbose = True;
 
     // doCommit rule: deq < wrongSpec (overwrite deq in doCommit) < doRenaming rule: enq
     Integer valid_deq_port = 0;

src_Core/RISCY_OOO/procs/lib/ReservationStationEhr.bsv

@@ -85,7 +85,7 @@ module mkReservationStation#(Bool lazySched, Bool lazyEnq, Bool countValid)(
     Add#(1, b__, size)
 );
 
-   Bool verbose = False;
+   Bool verbose = True;
 
     Integer valid_wrongSpec_port = 0;
     Integer valid_dispatch_port = 0; // write valid