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Changes to build with a 512-bit main data bus (with all other busses

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still 64-bits).
Also, the top-level SoC_Top exposes a 64-bit bus still, so hopefully the
GFE configuration is unchanged.
This passes the isa_tests.
This commit is contained in:
Jonathan Woodruff
2022-11-11 17:52:32 +00:00
parent 066289f8aa
commit ddf4afaf71
8 changed files with 41 additions and 29 deletions
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4
builds/Resources/Include_Common.mk
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@@ -88,11 +88,11 @@ BSC_COMPILATION_FLAGS += \
-D MULT_SYNTH \
-D Near_Mem_Caches \
-D FABRIC64 \
-D CheriBusBytes=8 \
-D CheriBusBytes=64 \
-D CheriMasterIDWidth=1 \
-D CheriTransactionIDWidth=6 \
-D CAP128 -D BLUESIM \
-D MEM64 \
-D MEM512 \
-D RISCV \
-D PERFORMANCE_MONITORING \
-D RAS_HIT_TRACING \

4
src_Core/CPU/Proc_IFC.bsv
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@@ -79,7 +79,7 @@ interface Proc_IFC;
Wd_AR_User, Wd_R_User) master0;
// Fabric master interface for IO (from MMIOPlatform)
interface AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data
interface AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data_Periph
, Wd_AW_User, Wd_W_User, Wd_B_User
, Wd_AR_User, Wd_R_User) master1;
@@ -106,7 +106,7 @@ interface Proc_IFC;
// ----------------
// Coherent port into LLC (used by Debug Module, DMA engines, ... to read/write memory)
interface AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data
interface AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data_Periph
, Wd_AW_User, Wd_W_User, Wd_B_User
, Wd_AR_User, Wd_R_User) debug_module_mem_server;

14
src_Core/Core/CoreW.bsv
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@@ -124,9 +124,9 @@ typedef WindCoreMid #( // AXI lite subordinate control port parameters
// AXI manager 0 port parameters
, TAdd #(Wd_MId, 1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0
// AXI manager 1 port parameters
, TAdd #(Wd_MId, 1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0
, TAdd #(Wd_MId, 1), Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0
// AXI subordinate 0 port parameters
, Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data
, Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data_Periph
, Wd_AW_User, Wd_W_User, Wd_B_User
, Wd_AR_User, Wd_R_User
// Number of interrupt lines
@@ -233,8 +233,10 @@ module mkCoreW_reset #(Reset porReset)
// handle cached interface
// AXI4 tagController
TagControllerAXI #(Wd_MId, Wd_Addr, Wd_Data)
tagController <- mkTagControllerAXI (reset_by all_harts_reset); // TODO double check if reseting like this is good enough
// tagController <- mkTagControllerAXI (reset_by all_harts_reset); // TODO double check if reseting like this is good enough
tagController <- mkFakeTagControllerAXI (reset_by all_harts_reset);
mkConnection (proc.master0, tagController.slave, reset_by all_harts_reset);
/*
`ifdef PERFORMANCE_MONITORING
rule report_tagController_events;
EventsCacheCore cache_core_evts = tagController.events;
@@ -251,7 +253,7 @@ module mkCoreW_reset #(Reset porReset)
proc.events_tgc(evts);
endrule
`endif
*/
// PLIC (Platform-Level Interrupt Controller)
PLIC_IFC_16_CoreNumX2_7 plic <- mkPLIC_16_CoreNumX2_7 (reset_by all_harts_reset);
@@ -459,7 +461,7 @@ module mkCoreW_reset #(Reset porReset)
// Masters on the local bus
Vector #( CoreW_Bus_Num_Masters
, AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data
, AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data_Periph
, Wd_AW_User, Wd_W_User, Wd_B_User
, Wd_AR_User, Wd_R_User))
master_vector = newVector;
@@ -470,7 +472,7 @@ module mkCoreW_reset #(Reset porReset)
// Slaves on the local bus
// default slave is forwarded out directly to the Core interface
Vector #( CoreW_Bus_Num_Slaves
, AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data
, AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data_Periph
, Wd_AW_User, Wd_W_User, Wd_B_User
, Wd_AR_User, Wd_R_User))
slave_vector = newVector;

3
src_Core/PLIC/PLIC.bsv
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@@ -385,9 +385,8 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority))
rdata = { rdata [31:0], 32'h0 };
// Send read-response to bus
Fabric_Data x = truncate (rdata);
let rdr = AXI4_RFlit {rid: rda.arid,
rdata: x,
rdata: rdata,
rresp: rresp,
rlast: True,
ruser: rda.aruser}; // XXX This requires that Wd_AR_User == Wd_R_User

2
src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv
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@@ -131,7 +131,7 @@ module mkLLCDmaConnect #( DmaServer#(LLCDmaReqId) llc
// REPLACED BY AXI4_Slave_interface
//, MemLoaderMemClient memLoader
, Vector#(CoreNum, TlbMemClient) tlb )
(AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data
(AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data_Periph
, Wd_AW_User, Wd_W_User, Wd_B_User
, Wd_AR_User, Wd_R_User))
provisos (Alias #(dmaRqT, DmaRq #(LLCDmaReqId)));

16
src_Testbench/SoC/Mem_Controller.bsv
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@@ -126,7 +126,7 @@ typedef TLog #(Word64s_per_Raw_Mem_Word) Bits_per_Word64_in_Raw_Me
// Type of index of a Word64 in a Raw_Mem_Word seen as a vector of Word64s
typedef Bit #(Bits_per_Word64_in_Raw_Mem_Word) Word64_in_Raw_Mem_Word;
typedef TDiv #(Bytes_per_Raw_Mem_Word, Bytes_per_Fabric_Data) Fabric_Data_per_Raw_Mem_Word;
typedef TDiv #(Bytes_per_Raw_Mem_Word, TDiv #(Wd_Data_Periph, 8)) Fabric_Data_per_Raw_Mem_Word;
// Index of bit that selects a fabric data word in an address
`ifdef FABRIC32
@@ -207,7 +207,7 @@ interface Mem_Controller_IFC;
method Action set_addr_map (Fabric_Addr addr_base, Fabric_Addr addr_lim);
// Main Fabric Reqs/Rsps
interface AXI4_Slave #(Wd_SId, Wd_Addr, Wd_Data, 0, 0, 0, 0, 0)
interface AXI4_Slave #(Wd_SId, Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0)
slave;
// To raw memory (outside the SoC)
@@ -245,8 +245,8 @@ typedef struct {Req_Op req_op;
Bit #(Wd_User) user;
// Write data info
Bit #(TDiv #(Wd_Data, 8)) wstrb;
Fabric_Data data;
Bit #(TDiv #(Wd_Data_Periph, 8)) wstrb;
Bit #(Wd_Data_Periph) data;
} Req
deriving (Bits, FShow);
@@ -487,7 +487,7 @@ module mkMem_Controller (Mem_Controller_IFC);
// We need to select the fabric data word from the raw mem word that contains the target address.
// View the raw mem word as a vector of fabric data words (Wd_Data width words)
Vector #(Fabric_Data_per_Raw_Mem_Word, Bit #(Wd_Data)) raw_mem_word_V_fabric_data = unpack (rg_cached_raw_mem_word);
Vector #(Fabric_Data_per_Raw_Mem_Word, Bit #(Wd_Data_Periph)) raw_mem_word_V_fabric_data = unpack (rg_cached_raw_mem_word);
// Get the index into this vector of the fabric word containing the target address.
// For this index, use a generous size (here Bit #(16)), and let zeroExtend pad it automaticallly.
@@ -496,7 +496,7 @@ module mkMem_Controller (Mem_Controller_IFC);
n = (n >> lo_fabric_data);
// Select the fabric data word of interest
Bit #(Wd_Data) rdata = raw_mem_word_V_fabric_data [n];
Bit #(Wd_Data_Periph) rdata = raw_mem_word_V_fabric_data [n];
let rdr = AXI4_RFlit {rid: f_reqs.first.id,
rdata: rdata,
@@ -529,7 +529,7 @@ module mkMem_Controller (Mem_Controller_IFC);
// Lane-adjust the new word64
Bit #(64) word64_new = zeroExtend (f_reqs.first.data);
Bit #(8) strobe = zeroExtend (f_reqs.first.wstrb);
if ((valueOf (Wd_Data) == 32) && (f_reqs.first.addr [2] == 1'b1)) begin
if ((valueOf (Wd_Data_Periph) == 32) && (f_reqs.first.addr [2] == 1'b1)) begin
// Upper 32b only
word64_new = { word64_new [31:0], 0 };
strobe = { strobe [3:0], 0 };
@@ -609,7 +609,7 @@ module mkMem_Controller (Mem_Controller_IFC);
rule rl_invalid_rd_address ( (rg_state == STATE_READY)
&& (! fn_addr_is_ok (rg_addr_base, f_reqs.first.addr, rg_addr_lim, f_reqs.first.size))
&& (f_reqs.first.req_op == REQ_OP_RD));
Fabric_Data rdata = zeroExtend (f_reqs.first.addr);
Bit#(Wd_Data_Periph) rdata = zeroExtend (f_reqs.first.addr);
let rdr = AXI4_RFlit {rid: f_reqs.first.id,
rdata: rdata, // for debugging only
rresp: SLVERR,

21
src_Testbench/SoC/SoC_Top.bsv
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@@ -153,15 +153,26 @@ module mkSoC_Top #(Reset dm_power_on_reset)
// SoC Boot ROM
Boot_ROM_IFC boot_rom <- mkBoot_ROM;
// AXI4 Deburster in front of Boot_ROM
AXI4_Shim#(Wd_SId, Wd_Addr, Wd_Data, 0, 0, 0, 0, 0)
AXI4_Shim#(Wd_SId, Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0)
boot_rom_axi4_deburster <- mkBurstToNoBurst;
// SoC Memory
Mem_Controller_IFC mem0_controller <- mkMem_Controller;
// AXI4 Deburster in front of SoC Memory
AXI4_Shim#(Wd_SId, Wd_Addr, Wd_Data, 0, 0, 0, 0, 0)
AXI4_Shim#(Wd_SId, Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0)
mem0_controller_axi4_deburster <- mkBurstToNoBurst;
// AXI4 Narrower Master in front of cached memory master
AXI4_Shim#(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0)
manager_0_narrow <- mkAXI4ShimFF;
AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, TDiv#(Wd_Data,4), 0, 0, 0, 0, 0)
manager_0_wide_a <- toWider_AXI4_Slave(manager_0_narrow.slave);
AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, TDiv#(Wd_Data,2), 0, 0, 0, 0, 0)
manager_0_wide_b <- toWider_AXI4_Slave(manager_0_wide_a);
AXI4_Slave #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0)
manager_0_wide <- toWider_AXI4_Slave(manager_0_wide_b);
mkConnection(corew.manager_0,manager_0_wide);
// SoC IPs
UART_IFC uart0 <- mkUART;
@@ -174,12 +185,12 @@ module mkSoC_Top #(Reset dm_power_on_reset)
// SoC fabric master connections
// Note: see 'SoC_Map' for 'master_num' definitions
Vector#(Num_Masters, AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data,
Vector#(Num_Masters, AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data_Periph,
0, 0, 0, 0, 0))
master_vector = newVector;
// CPU IMem master to fabric
master_vector[imem_master_num] = corew.manager_0;
master_vector[imem_master_num] = manager_0_narrow.master;
// CPU DMem master to fabric
master_vector[dmem_master_num] = corew.manager_1;
@@ -188,7 +199,7 @@ module mkSoC_Top #(Reset dm_power_on_reset)
// SoC fabric slave connections
// Note: see 'SoC_Map' for 'slave_num' definitions
Vector#(Num_Slaves, AXI4_Slave #(Wd_SId, Wd_Addr, Wd_Data,
Vector#(Num_Slaves, AXI4_Slave #(Wd_SId, Wd_Addr, Wd_Data_Periph,
0, 0, 0, 0, 0))
slave_vector = newVector;
Vector#(Num_Slaves, Range#(Wd_Addr)) route_vector = newVector;

6
src_Testbench/SoC/UART_Model.bsv
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@@ -130,7 +130,7 @@ interface UART_IFC;
method Action set_addr_map (Fabric_Addr addr_base, Fabric_Addr addr_lim);
// Main Fabric Reqs/Rsps
interface AXI4_Slave #(Wd_SId, Wd_Addr, Wd_Data, 0, 0, 0, 0, 0) slave;
interface AXI4_Slave #(Wd_SId, Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0) slave;
// To external console
interface Get #(Bit #(8)) get_to_console;
@@ -367,8 +367,8 @@ module mkUART (UART_IFC);
end
// Align data byte for AXI4 data bus based on fabric-width
Fabric_Data rdata = zeroExtend (rdata_byte);
if ((valueOf (Wd_Data) == 64) && (byte_addr [2:0] == 3'b100))
Bit#(Wd_Data_Periph) rdata = zeroExtend (rdata_byte);
if ((valueOf (Wd_Data_Periph) == 64) && (byte_addr [2:0] == 3'b100))
rdata = rdata << 32;
// Send read-response to bus