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Changes to build with a 512-bit main data bus (with all other busses

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still 64-bits).
Also, the top-level SoC_Top exposes a 64-bit bus still, so hopefully the
GFE configuration is unchanged.
This passes the isa_tests.
This commit is contained in:
Jonathan Woodruff
2022-11-11 17:52:32 +00:00
parent 066289f8aa
commit ddf4afaf71
8 changed files with 41 additions and 29 deletions
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4
src_Core/CPU/Proc_IFC.bsv
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@@ -79,7 +79,7 @@ interface Proc_IFC;
Wd_AR_User, Wd_R_User) master0;
// Fabric master interface for IO (from MMIOPlatform)
interface AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data
interface AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data_Periph
, Wd_AW_User, Wd_W_User, Wd_B_User
, Wd_AR_User, Wd_R_User) master1;
@@ -106,7 +106,7 @@ interface Proc_IFC;
// ----------------
// Coherent port into LLC (used by Debug Module, DMA engines, ... to read/write memory)
interface AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data
interface AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data_Periph
, Wd_AW_User, Wd_W_User, Wd_B_User
, Wd_AR_User, Wd_R_User) debug_module_mem_server;

14
src_Core/Core/CoreW.bsv
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@@ -124,9 +124,9 @@ typedef WindCoreMid #( // AXI lite subordinate control port parameters
// AXI manager 0 port parameters
, TAdd #(Wd_MId, 1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0
// AXI manager 1 port parameters
, TAdd #(Wd_MId, 1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0
, TAdd #(Wd_MId, 1), Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0
// AXI subordinate 0 port parameters
, Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data
, Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data_Periph
, Wd_AW_User, Wd_W_User, Wd_B_User
, Wd_AR_User, Wd_R_User
// Number of interrupt lines
@@ -233,8 +233,10 @@ module mkCoreW_reset #(Reset porReset)
// handle cached interface
// AXI4 tagController
TagControllerAXI #(Wd_MId, Wd_Addr, Wd_Data)
tagController <- mkTagControllerAXI (reset_by all_harts_reset); // TODO double check if reseting like this is good enough
// tagController <- mkTagControllerAXI (reset_by all_harts_reset); // TODO double check if reseting like this is good enough
tagController <- mkFakeTagControllerAXI (reset_by all_harts_reset);
mkConnection (proc.master0, tagController.slave, reset_by all_harts_reset);
/*
`ifdef PERFORMANCE_MONITORING
rule report_tagController_events;
EventsCacheCore cache_core_evts = tagController.events;
@@ -251,7 +253,7 @@ module mkCoreW_reset #(Reset porReset)
proc.events_tgc(evts);
endrule
`endif
*/
// PLIC (Platform-Level Interrupt Controller)
PLIC_IFC_16_CoreNumX2_7 plic <- mkPLIC_16_CoreNumX2_7 (reset_by all_harts_reset);
@@ -459,7 +461,7 @@ module mkCoreW_reset #(Reset porReset)
// Masters on the local bus
Vector #( CoreW_Bus_Num_Masters
, AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data
, AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data_Periph
, Wd_AW_User, Wd_W_User, Wd_B_User
, Wd_AR_User, Wd_R_User))
master_vector = newVector;
@@ -470,7 +472,7 @@ module mkCoreW_reset #(Reset porReset)
// Slaves on the local bus
// default slave is forwarded out directly to the Core interface
Vector #( CoreW_Bus_Num_Slaves
, AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data
, AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data_Periph
, Wd_AW_User, Wd_W_User, Wd_B_User
, Wd_AR_User, Wd_R_User))
slave_vector = newVector;

3
src_Core/PLIC/PLIC.bsv
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@@ -385,9 +385,8 @@ module mkPLIC (PLIC_IFC #(t_n_external_sources, t_n_targets, t_max_priority))
rdata = { rdata [31:0], 32'h0 };
// Send read-response to bus
Fabric_Data x = truncate (rdata);
let rdr = AXI4_RFlit {rid: rda.arid,
rdata: x,
rdata: rdata,
rresp: rresp,
rlast: True,
ruser: rda.aruser}; // XXX This requires that Wd_AR_User == Wd_R_User

2
src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv
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@@ -131,7 +131,7 @@ module mkLLCDmaConnect #( DmaServer#(LLCDmaReqId) llc
// REPLACED BY AXI4_Slave_interface
//, MemLoaderMemClient memLoader
, Vector#(CoreNum, TlbMemClient) tlb )
(AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data
(AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data_Periph
, Wd_AW_User, Wd_W_User, Wd_B_User
, Wd_AR_User, Wd_R_User))
provisos (Alias #(dmaRqT, DmaRq #(LLCDmaReqId)));