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Changes to build with a 512-bit main data bus (with all other busses

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still 64-bits).
Also, the top-level SoC_Top exposes a 64-bit bus still, so hopefully the
GFE configuration is unchanged.
This passes the isa_tests.
This commit is contained in:
Jonathan Woodruff
2022-11-11 17:52:32 +00:00
parent 066289f8aa
commit ddf4afaf71
8 changed files with 41 additions and 29 deletions
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4
src_Core/CPU/Proc_IFC.bsv
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@@ -79,7 +79,7 @@ interface Proc_IFC;
Wd_AR_User, Wd_R_User) master0;
// Fabric master interface for IO (from MMIOPlatform)
interface AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data
interface AXI4_Master #( Wd_CoreW_Bus_MId, Wd_Addr, Wd_Data_Periph
, Wd_AW_User, Wd_W_User, Wd_B_User
, Wd_AR_User, Wd_R_User) master1;
@@ -106,7 +106,7 @@ interface Proc_IFC;
// ----------------
// Coherent port into LLC (used by Debug Module, DMA engines, ... to read/write memory)
interface AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data
interface AXI4_Slave #( Wd_CoreW_Bus_SId, Wd_Addr, Wd_Data_Periph
, Wd_AW_User, Wd_W_User, Wd_B_User
, Wd_AR_User, Wd_R_User) debug_module_mem_server;